5nm Fab Challenges

New transistor types, plus issues with masks, patterning, materials, process control and interconnects, add up to a very tough transition.


At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry.

The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).

Intel may have telegraphed its intentions at 5nm, if not sooner. The paper signaled that Intel is exploring the idea of making a switch in transistor architectures down the road and is developing the technologies in the arena.

They’re not alone, of course. For example, Mark Liu, president and co-chief executive officer at TSMC, recently said that TSMC has begun work on 5nm, which it said will commence two years after 7nm. And in the R&D labs, others are looking at 5nm as well.

Needless to say, the timing and certainty of 5nm remain unclear. Chipmakers see a path to extend today’s finFETs to 7nm, but 5nm is far from certain and it may never happen. Indeed, there are a multitude of technical challenges at 5nm. And the cost for 5nm is expected to be astronomical.

But assuming that 5nm does happen at one time or another, the industry faces several roadblocks. “Everything is a challenge,” said Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. “You have physics and sensitivity requirements. You have the materials to deal with. You have the architectures that are changing.”

Others agree. “Performance and cost concerns are the big challenges in scaling to 5nm, and addressing them will involve the extension of current approaches as well as the introduction of new technologies and materials,” said Yang Pan, chief technology officer for the Global Products Group at LAM Research.

So, if the industry moves forward with 5nm, what are the challenges? To help the industry get ahead of the curve, Semiconductor Engineering has assembled a list of some of the more challenging process steps at 5nm.

Transistor options
But first, chipmakers must make some tough decisions. For one thing, they must select the right transistor architecture for 5nm. Today, there are two leading options—the finFET and the nanowire FET.

“FinFETs are one of the options for 5nm,” said Srinivasa Banna, a fellow and director of advanced device architecture at GlobalFoundries. “We would like to extend it. We’ve invested so much money in creating the infrastructure and an optimized device.”

Scaling the finFET to 5nm is challenging, however. In a 5nm finFET, for example, the fin width is projected to be 5nm, which is supposedly the theoretical limit for this structure.

That’s why chipmakers are exploring the nanowire FET. “Nanowires have good electrostatics,” Banna said. “But it does come with other issues, such as what is the device width of the nanowires and how much current can you get out of that device. Those are the areas that people are flushing out.”

Today, it’s still too early to select the winner between the finFET or nanowire FET at 5nm. “We are looking at a lot of options,” said Mark Rodder, senior vice president of the Advanced Logic Lab at Samsung. “There are many options and issues.”

Mask making
In the process flow, meanwhile, photomask manufacturing is one of the first steps. As before, lithography determines the mask type and specs. So if 5nm happens, the photomask industry will likely need to develop masks for two lithography types—optical and extreme ultraviolet (EUV) lithography.

Making an optical mask will be daunting at 5nm. Bringing up an EUV mask line is also difficult. “EUV masks are very different from 193i masks in many ways,” said Aki Fujimura, chief executive of D2S. “Because it is such a massive change, it will have a huge impact on the features, or capabilities, of every product in the supply chain. This includes resists, masks and pellicles, as well as the equipment like the e-beam writers and even software.”

On the EUV mask front, the industry is making progress in some areas, but not in others. Mask blank inspection is a bright spot. EUV mask inspection and pellicles are question marks.

For 5nm, though, mask write times will be the biggest challenge. The problem? Today’s single-beam e-beam tools are unable to pattern complex masks fast enough and in a cost-effective manner.

There is a solution. Two groups, the IMS/JEOL duo and NuFlare, are separately working on a new class of multi-beam e-beam mask writers. The tools, which promise to accelerate write times, are expected to ship in 2016.

Reports have surfaced, however, that the development of these tools are taking longer than expected due to technical issues. “Any disruptive new technology like this will take time to mature before it reaches high-volume production,” D2S’ Fujimura said.

After the mask is made, it is shipped to the fab. The mask is placed in a lithography tool. Then, the tool projects light through the mask, which, in turn, patterns the images on a wafer.

Needless to say, patterning is one of the big question marks at 5nm. For this, chipmakers hope that EUV is finally ready by 7nm and 5nm. This, of course, depends on the status of the power source, resists and mask infrastructure.

In theory, EUV will simplify the patterning process, thereby reducing cost. But even if EUV happens at 7nm and/or 5nm, chipmakers would require a form of multiple patterning.

Here’s a worse scenario: If EUV misses the window at 7nm and/or 5nm, chipmakers will hit a roadblock. It’s possible to extend today’s 193nm immersion to 7nm and beyond, but chip-manufacturing costs will become even more astronomical.

“A 5nm process with EUV should be cheaper than a 5nm process without it, but either version may be so expensive that increasingly fewer companies could afford it,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics.

At 5nm, though, chipmakers would likely implement a mix-and-match strategy. “The arrival of EUV will not mean the end of multi-patterning,” Abercrombie said. “By the time 5nm arrives, assuming EUV is ready for primetime, you will most likely see a mix of 193i single- and multi-patterning, single-pattered EUV and potentially multi-patterned EUV.

“It will be layer-specific. Some of the very simple, large-dimension layers will still be printable with single-patterned 193i. I believe that at least double-patterned 2LE 193i will still be cheaper than single-patterned EUV. Potentially even triple-patterned 3LE 193i may be cheaper for some layers. SADP will also be cheaper than single-patterned EUV,” he said. “EUV should be cheaper than 4LE or 5LE. So, it would be used in place of those on appropriate layers. It may be used in place of SAQP alternatives as well. The most critical of layers may have dimensions so tight that it would require double-patterned 2LE EUV.”

There are other issues as well. To extend EUV beyond 7nm, the technology may require a high numerical aperture (NA) lens as a means to boost the magnification of the scanner. For this, ASML is developing an anamorphic lens for EUV. The two-axis EUV lens would support 8x magnification in the scan mode and 4x in the other direction. It would support 0.5 to 0.6 NAs.

The problem? The EUV scanner could take a throughput hit. It would expose the wafer at only half the field size, as opposed to full field sizes with today’s EUV scanners.

Still, the question is clear—what if EUV misses 5nm or the technology fails? “5nm can be done without EUV,” Mentor’s Abercrombie said. “It would take a combination of more restrictive design and more complex multi-patterning. You may see five-patterned 5LE, SAQP with multi-patterned cuts, and of course, more layers in total needing multi-patterning. It will all come down to cost.”

Transistor materials
In the fab, the next step is to fabricate the transistor. Today, chipmakers are making finFETs at 16nm/14nm, with 10nm finFETs just around the corner.

Nanowire FETs share many of the same process steps as the finFET. In a nanowire FET, the wires run from the source, and through the gate, to the drain. The initial nanowire FETs would consist of three stacked wires.

By 5nm, a potential transistor type may require a boost. “New channel materials with higher electron or hole mobility may be required to achieve the required transistor performance,” Lam’s Pan said. “New technologies to reduce contact resistance and parasitic capacitance are also being developed to deliver required power and speed.”

For example, take Intel’s proposed nanowire FET. In the lab, Intel looked at different channel materials that would perform better than silicon. For the best drive current, germanium (Ge) is ideal for both NMOS and PMOS; meanwhile, for the lowest capacitance and power, Ge is ideal for PMOS, while III-V performs best for NMOS, according to Intel.

The problem? “III-V, high Ge and pure Ge all suffer from bandgap issues. So, there is leakage. Ge and III-V have reliability problems in the gate stack, which haven’t been solved yet,” said Michael Chudzik, senior director of strategic planning at Applied Materials.

Basically, the next step is the flow is the backend-of-the-line (BEOL). The BEOL is where the interconnects are formed within a device. Interconnects are tiny wiring schemes in devices and they are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.

The problems are escalating at each node. The industry is exploring different materials to solve the interconnect problem, but there are no obvious solutions at 7nm and beyond.

“The biggest change was when we went to multiple patterning at the backend. Then, the cost of the backend skyrocketed. That means now everyone is very careful from moving node to node,” said Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec.

And unless there is a major breakthrough in the BEOL, the problem goes from bad to worse at 5nm. “It’s many, many layers of multiple patterning. The backend features are really small,” Thean said.

Process control
During the flow, the chip must undergo various inspection steps. The challenge? Optical inspection, the workhorse technology in the fab, is struggling to detect defects at 20nm and below. And e-beam inspection can find tiny defects, but the technology is slow.

To solve the problem, the industry is working on multi-beam e-beam inspection, but this technology might not be ready until 2020.

So what’s the solution at 7nm and 5nm? “In theory, you have to do all of the above,” Applied Materials’ Vaez-Iravani said.

Meanwhile, metrology is another concern. In fact, there is no single metrology system that can measure everything. So, chipmakers must use several different metrology tools in the flow. “As the industry moves from one design node to the next, the challenges for metrology tools, whether optical or electron-beam, have always included: signal-to-noise ratios, accuracy, matching ease-of-use and production worthiness,” said Ady Levy, vice president of the Patterning 5D and Marketing Divisions at KLA-Tencor.

That’s not all. “For interconnects, high line and via resistance and greater variation due to surface scattering will drive the adoption of low-resistivity metals and development of process solutions to deliver much tighter process control,” Lam’s Pan said. “The adoption of next-generation lithography, such as EUV, and extension of multiple patterning techniques to enable these next-generation devices will require greater process control to achieve acceptable yield as well as addressing cost challenges for economical production.”

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Andy Mehdi says:

Excellent article!
As we know that KLA-Tencoe already dismissed their EUV roadmap after 5+ years of investment, I doubt that EUV will be to go to lithography (at least for the next 7 years). Just can not justify the cost.

susumu kuwabara says:

How about FD-SOI devices scaling ?

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