5nm Vs. 3nm

Half nodes, different transistor types, and numerous other options are adding uncertainty everywhere.


Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between.

The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm and 4nm. Moving to any of these nodes is very expensive, and benefits are not always clear-cut.

Another point of concern is the shrinking manufacturing base. There are fewer foundries to choose from at the most advanced nodes. The foundry industry once had several leading-edge vendors, but over time the field has narrowed due to soaring costs and a dwindling customer base. Generally, fewer vendors translates into fewer technical and pricing options.

Today, Samsung and TSMC are the only two foundries capable of providing processes at 7nm and beyond, although that could change. Intel and China’s SMIC are developing advanced processes. Intel, a bit player in the commercial foundry business, has struggled to ship 10nm. And it’s unclear if SMIC will ever ship 7nm, which is in R&D. (Intel’s 10nm process is similar to 7nm from the foundries.)

At advanced nodes, meanwhile, Samsung and TSMC are shipping 7nm processes using today’s finFET transistors, and both vendors will extend the finFET to 5nm. Compared to traditional planar transistors, finFETs are 3D-like structures with better performance and lower leakage.

Then, at 3nm, Samsung is making a transition from finFETs to a new transistor architecture called a nanosheet FET, which is an evolution of a finFET. TSMC, meanwhile, hasn’t disclosed its 3nm plans, leaving many foundry customers in a holding pattern. TSMC apparently is evaluating several options, including nanosheets, nanowires and souped-up finFETs, sources said. Intel, TSMC and others are also working on new forms of advanced packaging as a possible scaling option.

Nonetheless, transistor technology could go in various directions at 3nm. FinFETs are still in play, but the technology requires some breakthroughs. In all likelihood, the industry may need to get ready for a transition to a new architecture at 3nm and/or the next half-node at 2nm, according to the roadmap from one organization with visibility in the landscape.

“5nm is still a finFET,” said Naoto Horiguchi, logic program director at Imec. “Then, let’s say at N3, we are entering a transition period from finFETs to other device architectures. We believe it’s a nanosheet.”

A nanosheet FET is a type of gate-all-around (GAA) architecture. That’s not the only possible scenario. “The industry is very conservative. They will try to extend the finFET as much as possible,” Horiguchi said. “At 3nm, we have a window to use a finFET. But we need several process innovations for finFET in terms of overall improvement.

So do chipmakers stay at 7nm or migrate to 5nm, 3nm or to a new half-node? 7nm provides enough performance for most apps, which is why it will be a long-running node. Beyond 7nm, there are several high-performance options on the table, all with higher costs. And it remains to be seen if these new technologies will appear on time.

Figure 1: Planar transistors vs finFETs vs nanosheet FET. Source: Samsung

Foundry shakeout
A chip consists of a multitude of transistors, which serve as a switch in a device. For decades, the IC industry kept pace with Moore’s Law, the axiom that states transistor density in a device would double every 18 to 24 months.

So at this cadence, chipmakers introduced a new process technology with more transistor density, enabling the industry to lower the cost per transistor. At each node, chipmakers scaled the transistor specs by 0.7X, enabling the industry to deliver a 40% performance boost for the same amount of power and a 50% reduction in area.

Following this formula, the IC industry thrived. Starting in the 1980s, for example, it paved the way towards faster PCs at lower prices.

By 2001, there were more than 18 chipmakers with fabs that could process 130nm chips, which was the leading-edge process at the time, according to IBS. At that time, there were also several emerging foundry vendors that produced chips for others at mainly mature nodes in older fabs. Foundries also made chips for fabless design houses.

By the end of that decade, fab and process costs escalated. Unable to afford the costs, many chipmakers moved to a “fab lite” model. In other words, they produced some chips in their own fabs, while outsourcing some production to foundries.

Over time, fewer chipmakers produced leading-edge devices in their own fabs. Some went fabless or exited the business.

Nonetheless, the foundry model took off starting in the 2000s. Foundries were behind Intel and others in technology, but they still gave design houses access to various processes.

The next big change occurred at 20nm, when traditional planar transistors hit the wall and encountered short-channel effects. In response, Intel in 2011 moved to a next-generation transistor technology called finFETs at 22nm. The foundries moved to finFETs at 16nm/14nm.

FinFETs have several advantages over planar transistors. “In this scheme, the entire transistor is stretched in the vertical direction so that the channel is raised out of the substrate and the gate wraps around the three sides of the fin. The gate’s larger contact area in a certain 2D footprint allows better control of leakage current,” according to Matt Cogorno and Toshihiko Miyashita from Applied Materials in a blog. Cogorno is director of global product management, while Miyashita is a senior member of the technical staff.

FinFETs are also more complex devices, which are difficult to manufacture and scale at each node. As a result, process R&D costs have skyrocketed. So now, the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer.

IC design costs also continue to rise. The cost to design a 28nm planar device ranges from $10 million to $35 million, according to Gartner. In comparison, the cost to design a 7nm system-on-a-chip (SoC) ranges from $120 million to $420 million, according to Gartner.

“Design costs vary widely by the complexity of the SoC,” said Samuel Wang, an analyst at Gartner. “About two-thirds involve hardware chip design. The rest of the cost includes software development, mask costs and yield improvement. Design costs also come down over time.”

Nonetheless, the cost trends have altered the IC landscape. Over time, fewer IC companies could afford the design costs at the most advanced nodes. Many of these companies now rely on foundries for their production needs.

Fewer customers, coupled with soaring manufacturing costs, have impacted the leading-edge foundry landscape. For example, there are five chipmakers/foundries in the 16nm/14nm market—GlobalFoundries, Intel, Samsung, TSMC and UMC. SMIC also is working on 14nm finFETs.

But at 7nm, there was another shift. Process and manufacturing costs continued to escalate, but the return on investment was questionable. As a result, GlobalFoundries and UMC last year halted their respective 7nm process efforts. Both companies are still active in the 16nm/14nm market.

Going forward, Samsung and TSMC are moving full speed ahead at 7nm and beyond. And after repeated delays, Intel plans to ship 10nm by mid-2019, with 7nm slated for 2021. SMIC, meanwhile, has not announced a time frame.

But not all foundry customers require advanced nodes. There is still a thriving market for 28nm and above. “It depends on the product offering,” Gartner’s Wang said. “Some products require the highest performance. Designers can still use legacy nodes. Designs with non-demanding processes can live with the N-1 and N-2 nodes.”

Others agree. “From an economic standpoint, how many companies can afford silicon at the bleeding edge nowadays? That number is shrinking. For the very, very high performance markets, there is always going to be that need. But in the supply chain, from a volume standpoint, the chasm is opening up in the middle. The very leading edge needs 7, 5 and maybe 3nm someday. But everyone else has slowed down quite a bit,” said Walter Ng, vice president of business management at UMC.

Still, there is a need for leading-edge chips in select applications, such as servers and smartphones. Then, a plethora of new AI chip startups are surfacing. Many are designing chips for machine learning and deep learning.

“There’s no question that being able to compute 10x faster than now will be commercially useful and competitively required, even for non-technical markets. All of deep learning’s unique accomplishments are evidence of that. There’s virtually no end in sight for the demand for more computing power,” said Aki Fujimura, chief executive of D2S.

“The need for compute power went through several large shifts, first with GPUs and then more recently with deep learning,” Fujimura said. “Deep learning is a massive pattern-matching technology, where neural network training is an iterative optimization problem. Now that the world has figured out a mechanism to handle massive amounts of data and turn it into useful information in the form of an inferencing program, the amount of computing needed scales with the amount of data available. Since available data for all problem domains are each increasing geometrically, it is virtually guaranteed that the computing power required will increase substantially just to handle the deep-learning loads.”

Whether AI chips require 5nm and beyond processes remains unclear, but there is certainly a need for more compute power. Still, it isn’t getting any easier or less expensive to migrate to these nodes.

5nm vs 3nm
Meanwhile, TSMC reached a major milestone in early 2018, when it became the world’s first vendor to ship 7nm. Later, Samsung entered the 7nm race. Generally, based on finFETs, a 7nm foundry process consists of a 56nm to 57nm gate pitch and a 40nm metal pitch, according to IC Knowledge and TEL.

In its first version of 7nm, TSMC used 193nm immersion lithography and multiple patterning. Later this year, TSMC will ship a new version of 7nm using extreme ultraviolet (EUV) lithography. EUV simplifies the process steps, but it’s an expensive technology with its own set of challenges.

Now, TSMC is readying its new 5nm process for the first half of 2020. TSMC’s 5nm technology is 15% faster with 30% lower power than 7nm. A second version of 5nm, due out next year, is 7% faster. Both versions also will use EUV.

TSMC is gaining some traction for 5nm. “Apple, HiSilicon and Qualcomm are expected to be in high volume at 5nm in 2020,” said Handel Jones, chief executive of International Business Strategies (IBS). “Wafer volumes will be 40,000 to 60,000 wafers per month by the fourth quarter of 2020.”

The adoption rate for TSMC’s 5nm is slower than 7nm. For one thing, 5nm is a completely new process with updated EDA tools and IP. In addition, it costs more. Generally, the cost to design a 5nm device ranges from $210 million to $680 million, according to Gartner.

Some chipmakers want a migration path from 7nm without the high cost of 5nm. So TSMC recently introduced a new half-node option called 6nm, which is a lower-cost option with some tradeoffs.

“The numbers N6 and N5 look pretty close, but they still have a big gap,” said C. C. Wei, chief executive of TSMC, in a recent conference call. “For N5 compared with N7, the logic density increased by 80%. N6 compared with N7 is only 18%. So you can see there’s a big difference in that logic density and transistor performance. And so as a result, the total power consumption in the chip is lower in the N5. There’s a lot of benefit if you move into N5. But nevertheless, N5 is one full node, and it takes time for the customer to design their new products. The beauty of the N6 is if they already designed in N7, they spend a very minimal effort. They can move into the N6 and gain some benefit. Depending on their product characteristics and their market, (customers) will decide which one to go to.”

Meanwhile Samsung recently rolled out 5nm, which is due out in the first half of 2020. Compared to 7nm, Samsung’s 5nm finFET technology provides up to a 25% increase in logic area with 20% lower power or 10% higher performance.

Samsung also introduced a new 6nm half-node, giving customers another option. “6nm has the scalability benefit from 7nm and the IP can be reused,” said Ryan Lee, vice president of marketing for the foundry business at Samsung. Then, on its roadmap, Samsung also is developing a 4nm finFET process. So far, there is little public information about this technology.

After 5nm, the next full node is 3nm. But 3nm is not for the faint of heart. The cost to design a 3nm device ranges from $500 million to $1.5 billion, according to IBS. Process development costs ranges from $4 billion to $5 billion, while a fab runs $15 billion to $20 billion, according to IBS. “Transistor costs at 3nm are expected to be 20% to 25% higher than at 5nm based on same level of maturity,” IBS’ Jones said. “Expect 15% more performance and with 25% less power consumption compared to 5nm finFETs.”

Samsung is the only company that has announced its 3nm plans so far. For that node, the foundry will move to a new gate-all-around technology called the nanosheet. TSMC has yet to disclose its plans, leaving some to believe that it’s behind the curve. “At 3nm, Samsung has a high probability of initial high-volume production in 2021,” Jones said. “TSMC is accelerating the development to try to close the gap with Samsung.”

At 3nm, TSMC is looking at nanosheet FETs, nanowire FETs and even finFETs, according to sources. One way to extend finFETs is by using high-mobility materials in the channels, namely germanium. Today’s finFET devices use silicon or silicon-germanium (SiGe) in the channel. A larger germanium mix can be used to boost the channel mobility, which refers to how fast the electrons can move through a device. Controlling the defects is the challenge here.

Extending the finFET makes sense. A 3nm finFET provides a migration path from today’s 5nm finFETs. But there are some challenges, too. In theory, the finFET hits its limit when the fin width reaches 5nm, which is close to where it is today. “Today, we are using two fins for NMOS and two fins for PMOS in a standard cell,” Imec’s Horiguchi said. “In one important aspect of 3nm, we need to go to a single fin architecture in terms of a standard cell design. The single fin must have enough drivability. To extend the finFET to N3, we need a special technique to enhance the single fin power and/or reduce backend parasitics.”

Besides a high mobility finFET, the next option on the table is gate-all-around. In 2017, Samsung introduced the so-called Multi Bridge Channel FET (MBCFET) for 3nm. MBCFET is a nanosheet FET. Samsung’s first MBCFET will move into risk production in 2020.

Nanosheets have some advantages over finFETs. In finFETs, the gate is wrapped around on three sides of a fin. In nanosheets, the gate is on four sides of the fin, enabling more control of the current.

Compared to 5nm, Samsung’s nanosheet FET provides up to a 45% increase in logic area efficiency with 50% lower power consumption or 35% higher performance. “The finFET structure has some limit in terms of scalability, because the supply voltage can’t be reduced below 0.75. We made an innovation using this nanosheet structure to reduce the supply voltage under 0.7 volt,” Samsung’s Lee said.

There are several types of gate-all-around technologies, including nanosheet FETs and nanowire FETs. Gate-all-around itself is an evolutionary step from the finFET. In gate-all-around, a finFET is placed on its side and is then divided into separate horizontal pieces. Each separate piece makes up the channels. A gate material wraps around each sheet.

Compared to the nanowire FET, the nanosheet FET has a wider channel, which translates into more performance and drive current. “The nanosheet has a larger effective width,” Imec’s Horiguchi said. “The nanowire is very good for the electrostatics. But the cross section is rather small. That will not bring an advantage for the effective channel width.”

There are several challenges with gate-all-around architectures. Generally, they provide only a modest scaling boost over 5nm finFETs. And making gate-all-around technology in the fab is challenging.

“When you start the next generation of gate-all-around at 3nm and below, that’s another order of magnitude in complexity,” said Richard Gottscho, executive vice president and CTO of Lam Research. “At first, it looks like a modification of a finFET. But the requirements are getting tightened, and the complexity of that gate-all-around architecture is significantly greater than the finFET.”

In the nanosheet process flow, the first step is to deposit thin and alternating layers of SiGe and silicon on a substrate. “In this case, you have a silicon, silicon germanium and silicon stack. We call it a superlattice,” said Namsung Kim, senior director of engineering management at Applied Materials, in a recent interview. “Since we have germanium content, we need to have a good shielding liner layer.”

At a minimum, a stack would consist of three layers of SiGe and three layers of silicon. Then, you pattern tiny sheet-like structures on the stack. Following that, a shallow trench isolation structure is formed, followed by the development of inner-spacers.

Then, the SiGe layers are removed in the super-lattice structure, leaving the silicon layers with a space between them. Each silicon layer forms the basis of a sheet or channel in the device. The next step is to deposit a high-k material for the gate. “In between the nanowires, there is minimum separation. The distance is very small. The challenge is how do you deposit the workfunction metal thickness,” Kim said.

The industry has been working on gate-all-around for years, but there are still some challenges. “One of the main challenges is parasitic capacitance,” Kim said. “If you ask me what are the top challenges in gate-all-around technology, there are two. One is the inter-spacer and then the bottom isolation.”

What’s next?
So how far will gate-all-around or nanosheets extend? “The nanosheet can extend probably two or three nodes. A foundry can introduce a nanosheet at N3. The next generation is probably for sure. After that we might have to change the nanosheet integration or architecture. But it’s still a nanosheet architecture,” Imec’s Horiguchi said.

In R&D, the industry is working on ways to improve gate-all-around and finFETs at advanced nodes. At this point, gate-all-around devices provide only a modest scaling boost over finFETs. For example, Imec’s previous nanosheet had a gate pitch of 42nm and a metal pitch of 21nm. In comparison, a 5nm finFET may have a 48nm gate pitch with a 28nm metal pitch.

In the lab, Imec has demonstrated the scalability of a p-type, double stacked gate-all-around device with germanium in the channel. Using an extension-less scheme, Imec developed a nanowire with a gate length of around 25nm. That can also be tuned for a nanosheet. Like the previous version, the wire dimensions are 9nm.

Germanium could play a role to extend the finFET beyond 5nm. Imec demonstrated Ge nFinFETs with a record high Gmsat/SSsat and PBTI reliability. This was done by improving the replacement gate high-k process.

Still to be seen, however, is whether finFET technology will extend to 3nm. It’s also unclear if nanosheets will appear on time. In fact, there are many unknowns and uncertainties in the changing landscape, and no firm timetable for when there will be more clarity.

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Rand Walker says:

Many thanks Mark. As a non-practitioner, I found this overview very valuable. For me at least, the accessible/informative balance was just right.

miro says:

A great overview! Many thanks.

Kalle says:

Wonderful and detailed, expert analysis, which was relatively easy to read for an hobbyist. Thank you!

Piotr Grabowski says:

A very clear and informative article. Many thanks Mark!

David Leary says:

Something that is not scaling is the reliability expectation of 10-year service life of ICs in the server and switching applications. It’s unclear that 7nm is capable of 10-year lifetime in ASIC use conditions. I’d like to see articles on N+ silicon technologies address how reliability challenges are being assessed and mitigated.

Krishna Kireeti says:

Such a great detailed and informative article. Many thanks.

Marc-David Levenson says:

The lattice spacing of silicon is 0.54 nm, so a 5nm Si structure is less than 10 lattice constants – about 20 nearest-neighbor atoms – across. Does anyone worry about that?

John Doering says:

Great article Mark! However, I’ve become confused over the definition of a node and am no longer sure if 7nm, 5nm or 3nm represent an actual CD . Can you clarify node definitions and if the “7nm” node is the same for TSMC, Samsung and Intel? Perhaps the industry needs a new measure to compare (MT/mm2)?

Mark LaPedus says:

Hi John, I agree with you. The nodes are confusing. Historically, a technology node name was based on a fraction of the tightest pitch used, typically the finest routed pitch (metal 2). See:

Now, the node names are arbitrary numbers. They are meaningless. Don’t look for any standards anytime soon.

However, the 7nm specs for TSMC and Samsung are somewhat the same. Intel’s 10nm is roughly equivalent to 7nm from the foundries. See:



Brian C. says:

Thank you, Mark, for producing one of the few articles of this length where it’s worth reading every word.

Gaurav Goel says:

Well written and informative. Thank you for publishing this article.

I am amazed, and I think many others would be as well, to learn that the US has already fallen behind Korea and Taiwan in the semiconductor foundry business.

Narendra says:

It is surprising to me that at 25% or 50% increase in the area people consider Moore’s law “alive”. It used to be that people doubled the number of transistors (or 100% area increase) every two years. Let’s solve a compound interest problem with 25%, 50% and, 100% increase every two years.
In 6 years,
with 100%, area = x*(1+ 1.00)^3 = 8 x
with 50%, area = x*(1 + 0.5)^3 = 3.375 x
with 25% area = x*(1 + 0.25)^3 = 1.95 x

In 20 years,
with 100%, area = x*(1+ 1.00)^10 = 1024 x
with 50%, area = x*(1 + 0.5)^10 = 57.66 x
with 25% area = x*(1 + 0.25)^10 = 9.31 x

Another way to look at it is that with a 25% rate, it will take 62 years to achieve the same area increase of the previous 20 years.

Why not just admit that Moore’s law is over? Yes, we are still going to improve but that’s not same as Moore’s law.

Glen Waldrop says:

I don’t get people’s need to say that Intel’s 10nm is close to TSMC or Samsung’s 7nm.

Look up the actual specs of the lithography from 22nm and down, they’re really not that different and the one major difference between TSMC and Samsung’s 7nm vs Intel’s 10nm is that 7nm is actually on target, in volume production and profitable already.

Intel is losing money on 10nm horribly, performance isn’t good, clock speeds are low and power usage is high.

10nm+ and Ice Lake may be the product Intel needs, but it is still mobile only. Intel’s 10nm is nowhere near their competitor’s 7nm *because it barely works after they threw away the first version and started over*.

Intel was so determined to have their 10nm be better than everyone else’s 7nm *that it didn’t even work*.

Glen Waldrop says:

Narendra, the quote was “the principle that the speed and capability of computers can be expected to double every two years, as a result of increases in the number of transistors a microchip can contain.”

It had nothing to do with lithography per sq mm. You’re misunderstanding the law, not disproving it.

He also only expected that to hold true for a couple years. He has said so in multiple interviews. We are, however, coming near the end of lithography improvements. The electromagnetic field of an electron is like 1-2nm, higher voltage and amperage increases this, so it is going to become far more difficult from here on.

That being said, we’re not actually where the majority of the parts are 7nm, most are much larger, a couple are smaller.

There also is the point that the circuits feeding the transistors have to be bigger to deliver amperage to the transistor to enable switching, smaller = hotter = more resistance = hotter = lower voltage = more amperage = hotter.

It’s going to end, or at the very least no longer be economical.

Narendra says:

This is the article which Moore wrote in 1965.

I am not misunderstanding the law. It is about the number of components (transistors) per integrated circuit for minimum cost. The cost is determined from yield which depends on the area of IC. So, Moore’s law states that you double the number of transistor per unit area. It is the same as saying 100% area increase every two years.

It will take Intel a full 5 years (14nm shipped at the end of 2014) to achieve this task when they ship 10nm.

There is also an interesting paragraph in Moore’s article where he talks about the “Day of reckoning” or end of the trend. He basically said that trend is over when you start seeing chiplet type design. Exact words “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”

The issue is that the marketing department of companies will never admit that Moore’s law is over. The management doesn’t admit it because they may have to explain bad bets on unprofitable technologies.
So their philosophy towards R&D is this, “beatings will continue until the morale improves”.

clh says:

My experience in working on both 14nm and 7nm in both Samsung and TSMC … Samsung is always an easier design. It seems the verification decks for TSMC are always done by non users or something … more complicated to interpret than necessary.

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