Week In Review: Manufacturing, Test


Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

Week In Review: Manufacturing, Test


Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Challenges Grow For 5G Packages And Modules


The shift to 5G wireless networks is driving a need for new IC packages and modules in smartphones and other systems, but this move is turning out to be harder than it looks. For one thing, the IC packages and RF modules for 5G phones are more complex and expensive than today's devices, and that gap will grow significantly in the second phase of 5G. In addition, 5G devices will require an as... » read more

5nm Vs. 3nm


Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Week In Review: Manufacturing, Test


Packaging and test In the rankings, ASE was the top OSAT in terms of sales in the first quarter of 2019, according to TrendForce. Amkor and JCET were next in the rankings. “Judging from the falling phone sales 1Q19 impacted by the U.S.-China trade dispute and the oversupply situation in memory markets, the total revenue of the top ten businesses in packaging and testing are predicted to st... » read more

The Arm-Huawei Disconnect


Arm's move to stop licensing its processor IP to HiSilicon, the captive chipmaker for Huawei, has set off a panic across the semiconductor industry. While the underlying threat to the entire chip industry is very real, many of the conclusions being drawn about this move are misleading or just plain wrong. When the U.S. government blacklisted Huawei, it imposed export restrictions on shipping... » read more

Aging In Advanced Nodes


Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Using More Verification Cores


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Verification Trends Enabling A 5G Future


Applications have driven requirements for verification for quite some time now, as I have written previously regarding Aero & Defense, AI and Machine Learning and the Internet of Things. In wireless communication, we are just at the brink of the transition to Fifth Generation Networks, or 5G. This transition will not only lead to new applications and use models that will impact our day-to-d... » read more

Week In Review: Design, Low Power


Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

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