New Class Of Semiconductors Made Of Germanium-Tin Alloy (University of Edinburgh et al.)


A new technical paper "High Pressure and Compositionally Directed Route to a Hexagonal GeSn Alloy Class" was published by researchers at the University of Edinburgh, GFZ Helmholtz Centre for Geosciences, the University of Lille, Grenoble Alpes University, the University of Bayreuth and the European Synchrotron facility. Abstract "Despite their electronic dominance, cubic diamond structure... » read more

SiGeSn SBFETs at Cryogenic Temperatures (Tu Wien et al)


A new technical paper titled "A Cryogenic Ultra-Thin Body SiGeSn Transistor" was published by researchers at TU Wien, Johannes Kepler University, Universidad de Granada, and Max Planck Institute for Sustainable Materials. Abstract "Transistors capable of operating at cryogenic temperatures are key components for the fast and energy-efficient control and readout of qubits. However, the ultra... » read more

Research Bits: Dec. 16


Back-end integration Researchers from Massachusetts Institute of Technology (MIT) and the University of Waterloo propose a back-end integration platform that enables the fabrication of transistors and memory devices in a single compact stack on a chip. The approach uses amorphous indium oxide as the active channel layer of the back-end transistor. The properties of indium oxide allow a thin... » read more

Research Bits: Nov. 10


Post-doping plasma for DRAM capacitors Researchers from Ulsan National Institute of Science and Technology (UNIST), Pohang University of Science and Technology (POSTECH), and Seoul National University of Science and Technology developed a post-doping plasma (PDP) process to improve the performance of DRAM capacitors. Aluminum-doped titanium dioxide (Al-doped TiO2) is a promising material fo... » read more

Electrochemical Absorption of Hydrogen in Structured Palladium Thin-Film Electrodes (Univ. of Bristol)


A new technical paper titled "Exploring Electrochemical Methods for Precision Stress Control in Nanoscale Devices " was published by researchers at the University of Bristol. Abstract "Tuning the local film stress (and associated strain) provides a universal route toward exerting dynamic control on propagating fields in nanoscale geometries and engineering controlled interactions between th... » read more

Visualization of Photoexcited Charges Moving Across the Interface of Si/Ge


A technical paper titled "Imaging hot photocarrier transfer across a semiconductor heterojunction with ultrafast electron microscopy" was published by researchers at UC Santa Barbara and UCLA. "In this work, we apply scanning ultrafast electron microscopy to provide a holistic view of photoexcited charge dynamics in a Si/Ge heterojunction. We find that the built-in potential and the band off... » read more

Buried Si/SiGe Interfaces Investigated Using Soft X-Ray Reflectometry and STEM-EDX


A new technical paper titled "Interface sharpness in stacked thin film structures: a comparison of soft X-ray reflectometry and transmission electron microscopy" was published by researchers at Physikalisch-Technische Bundesanstalt (PTB), imec, and Thermo Fisher Scientific Inc. The paper states: "A key element of semiconductor fabrication is the precise deposition of thin films. Among other... » read more

Week In Review: Semiconductor Manufacturing, Test


SEMICON West returned in force this week, with a focus on AI and deep learning  in semiconductor manufacturing, security, heterogenous ICs, and the march toward a $1 trillion chip market. Lam Research President and CEO, Tim Archer, opened with the keynote presentation. Fig. 1: SEMICON West panel: AI’s influence on growth, China-U.S. trade war, and the importance of climate policy were... » read more

Epi SiGe Application Using METRION In-Line SIMS System


The epitaxial process is a well-established deposition technique in semiconductor fabrication because it enables the ability to achieve much higher doping concentrations than can be obtained via ion implantation. As we move toward <5nm technology, a key process for enabling gate-all-around FET (GAAFET) is the stacked multi-lattice of Silicon (Si) and Silicon-germanium (SiGe) epi process for ... » read more

Using More Germanium In Chips for Energy Efficiency & Achievable Clock Frequencies


A new technical paper titled "Composition Dependent Electrical Transport in Si1−xGex Nanosheets with Monolithic Single-Elementary Al Contacts" was published by researchers at TU Wien (Vienna University of Technology), Johannes Kepler University, CEA-LETI, and Swiss Federal Laboratories for Materials Science and Technology. Find the technical paper here. Published September 2022. Abstrac... » read more

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