Back-end integration; all-digital probabilistic computing; high-mobility germanium.
Researchers from Massachusetts Institute of Technology (MIT) and the University of Waterloo propose a back-end integration platform that enables the fabrication of transistors and memory devices in a single compact stack on a chip.
The approach uses amorphous indium oxide as the active channel layer of the back-end transistor. The properties of indium oxide allow a thin layer to be grown at a temperature of about 150 degrees Celsius on the back end of an existing circuit without damaging the device on the front end.
“If we can use this back-end platform to put in additional active layers of transistors, not just interconnects, that would make the integration density of the chip much higher and improve its energy efficiency,” said Yanjie Shao, an MIT postdoc, in a press release.
The team optimized the fabrication process to create a 2nm thick indium oxide layer with minimal defects to create a transistor. They added a layer of ferroelectric hafnium-zirconium-oxide to fabricate the memory component, resulting in back-end transistors with integrated memory that were about 20nm and demonstrated switching speeds of 10 nanoseconds at lower voltage than similar devices.
The team plans to use the memory transistors as a platform to study the fundamental physics of individual units of ferroelectric hafnium-zirconium-oxide. “If we can better understand the physics, we can use this material for many new applications. The energy it uses is very minimal, and it gives us a lot of flexibility in how we can design devices. It really could open up many new avenues for the future,” said Shao. “Now, we can build a platform of versatile electronics on the back end of a chip that enable us to achieve high energy efficiency and many different functionalities in very small devices. We have a good device architecture and material to work with, but we need to keep innovating to uncover the ultimate performance limits.” [1, 2]
Researchers from the University of California Santa Barbara, Tohoku University, and TSMC suggest using “probabilistic bits,” or “p-bits,” to improve the efficiency of AI compute. P-bits naturally fluctuate between 0 and 1, making them well-suited for solving problems such as optimization and inference.
While previous p-bit proposals included an analog component and DAC, the new research offers an all-digital p-bit design. “The reliance on analog signals was holding back progress,” said Shunsuke Fukami, a professor at Tohoku University, in a statement. “So, we discovered a digital method to adjust the behavior of p-bits without needing the typically used big, clunky analog circuits.”
The device uses magnetic tunnel junctions (MTJs), which naturally switch between two states in a random manner. By feeding this 50/50 random bitstream into a simple digital circuit that gradually combines signals with controlled timing, the researchers were able to smoothly tune how likely the output is to be 0 or 1.
The researchers noted that the system updates its internal state in a self-organizing manner, so different elements don’t interfere, enabling many p-bits to work in parallel without a central controller. It also allows a form of “on-chip annealing” to gradually narrow down solutions by changing basic timing settings rather than completely rewriting stored parameters. Additionally, the approach naturally compensates for manufacturing variations. [3]
Researchers from University of Warwick and National Research Council of Canada created a high-mobility semiconductor using a nanometer-thick compressively strained germanium epilayer on silicon. When evaluated, the material demonstrated a hole mobility of 7.15 million cm2 per volt-second.
“Traditional high-mobility semiconductors such as gallium arsenide (GaAs) are very expensive and impossible to integrate with mainstream silicon manufacturing. Our new compressively strained germanium-on-silicon (cs-GoS) quantum material combines world-leading mobility with industrial scalability — a key step toward practical quantum and classical large-scale integrated circuits,” said Maksym Myronov, associate professor and leader of the Semiconductors Research Group, Department of Physics, University of Warwick, in a statement. [4]
[1] Y. Shao, D. Ma, D. Antoniadis, et al. Enhancement-mode BEOL In2O3 FETs with Record Logic Performance: Experiments and Compact Modeling. IEEE IEDM 2025. https://mtlsites.mit.edu/users/alamo/pdf/2025/paper%201.pdf
[2] Y. Shao, M. Kim, J. Huang, et al. Single-domain Switching Dynamics in BEOL Nanoscale Ferroelectric Field-effect Transistors. IEEE IEDM 2025. https://mtlsites.mit.edu/users/alamo/pdf/2025/paper%202.pdf
[3] K. Selcuk, N. A. Aadit, C. Delacour, et al. DAC-Free p-bits: Asynchronous Self-Coloring and On-Chip Annealing. IEEE IEDM 2025. https://iedm25.mapyourshow.com/8_0/sessions/session-details.cfm?scheduleid=141
[4] M. Myronov, A. Bogan, S. Studenikin. Hole mobility in compressively strained germanium on silicon exceeds 7× 106 cm2V-1s− 1. Materials Today. https://doi.org/10.1016/j.mattod.2025.10.004
 |
 |
 |
 |
 |  |
 |  |
 |
Leave a Reply