Research Bits: Apr. 28


Parchment papertronics Researchers from Binghamton University used commercial parchment paper, commonly used in baking, along with a standard carbon dioxide laser and water-based conductive ink to create disposable, single-use electronic circuits. The laser selectively removes the paper's thin silicone coating in specific patterns, exposing the water-absorbing cellulose fibers underneath. T... » read more

Chip Industry Technical Paper Roundup: Mar. 3


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

Research Bits: Dec. 16


Back-end integration Researchers from Massachusetts Institute of Technology (MIT) and the University of Waterloo propose a back-end integration platform that enables the fabrication of transistors and memory devices in a single compact stack on a chip. The approach uses amorphous indium oxide as the active channel layer of the back-end transistor. The properties of indium oxide allow a thin... » read more

Chip Industry Technical Paper Roundup: Oct. 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=486 /] Find more semiconductor research papers here. » read more

Thermal Simulation And Optimization in 3D-IC Design (Intel, UCSB, Cadence)


A new technical paper titled "DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design" was published by researchers at Intel Corporation, University of California, Santa Barbara and Cadence. Abstract "Thermal analysis is crucial in 3D-IC design due to increased power density and complex heat dissipation paths. Although operator ... » read more

Research Bits: Sept. 23


Opto-electrical excitation of MTJs Researchers at the University of Greifswald, International Iberian Nanotechnology Laboratory, Max Planck Institute for the Science of Light, and Aarhus University advanced the use of magnetic tunnel junctions (MTJs) for neuromorphic computing. The team developed a hybrid opto-electrical excitation scheme that combines electrical currents with short laser p... » read more

Chip Industry Technical Paper Roundup: Sept 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=471 /] Find more semiconductor research papers here. » read more

HW Security: 2.5D and 3D Technologies Provide Opportunities in Designing Secure Systems (UCSB, Columbia)


A new technical paper titled "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges" was published by researchers at the University of California, Santa Barbara and Columbia University. Abstract "3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealin... » read more

Chip Industry Week in Review


Cadence plans to buy Hexagon AB's design and engineering business to accelerate expansion in physical AI and system design and analysis. Cadence will pay ~US$3.1 billion in cash and issue stock, with the deal expected to close in early 2026. PWC issued a 104-page in-depth analysis of semiconductor technology and markets, highlighting a broad swath of changes: $1T in annual revenue by 2030, ... » read more

Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

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