Why process, voltage and temperature are so interrelated at future nodes, and what impact that has on design.
Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI component or advanced packaging, which makes multi-physics analysis essential.
Increasing complexity, disaggregation, and continued feature shrinks add to problem; oversight is scant.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
Pitches continue to decrease, but new tooling and technologies are required.
Buried features and re-entrant geometries drive application-specific metrology solutions.
Issues involving design, manufacturing, packaging, and observability all need to be solved before this approach goes mainstream for many applications.
Existing tools can be used for RISC-V, but they may not be the most effective or efficient. What else is needed?
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Technical and business challenges persist, but momentum is building.
Gate-all-around is set to replace finFET, but it brings its own set of challenges and unknowns.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
Academia, industry partnerships ramp to entice undergrads into hardware engineering.
High speed and low heat make this technology essential, but it’s extremely complex and talent is hard to find and train.
The industry seems to think it is a real goal for the open instruction set architecture.
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