Multi-Physics At 5/3nm


Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

Taming NBTI To Improve Device Reliability


Negative-bias temperature instability is a growing issue at the most advanced process nodes, but it also has proven extremely difficult to tame using conventional approaches. That finally may be starting to change. NBTI is an aging mechanism in field-effect transistors that leads to a change of the characteristic curves of a transistor during operation. The result can be a drift toward unint... » read more

Process Corner Explosion


The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Minimizing The Risk Of Electromagnetic Crosstalk Failures


Leading semiconductor markets, such automotive, machine learning, large scale computing and networking, are driving the need for high density chips that integrate high performance digital cores with sensitive analog/RF IP, while operating at the lowest power and fastest bandwidth possible. These trends are increasing the sensitivity to electromagnetic (EM) coupling, and requiring designers to w... » read more