Taming NBTI To Improve Device Reliability

Negative-bias temperature instability can cause an array of problems at advanced nodes and reduced voltages.


Negative-bias temperature instability is a growing issue at the most advanced process nodes, but it also has proven extremely difficult to tame using conventional approaches. That finally may be starting to change.

NBTI is an aging mechanism in field-effect transistors that leads to a change of the characteristic curves of a transistor during operation. The result can be a drift toward unintended behavior by functional transistor circuits.

More specifically, NBTI can increase gate delay times in digital applications, which in turn can result in timing violations that corrupt calculation results. In analog circuits, even small changes of the FET characteristics can have a negative effect on circuit precision. For instance, matching-pair FETs might age differently and lead to inaccuracies in analog-to-digital converters, explained Kay-Uwe Giering, research associate at Fraunhofer EAS.

“An additional complication is that the small FETs of advanced technology nodes face the problem of NBTI variability, whereas the number of NBTI-relevant defects decreases with gate oxide area,” said Giering. “The defect properties remain widely spread, such that FETs of the same geometry can age very differently. Hence, the NBTI degradation is subject to a statistical variability, which would have averaged out in larger transistors.”

The rate of threshold voltage (Vt) drift from NBTI accelerates at high voltages—which may be required for many designs to meet their performance targets—and at higher temperatures, which are driven by high-frequency switching activity and local thermal effects, noted Jim Dodrill, senior technical director for the Physical Design Group at Arm. “The timing effects are most pronounced when the device voltage is then reduced for low-power operation.”

Magdy Abadir, vice president of marketing at Helic, agreed. “As devices age, NBTI increases the threshold voltage in PMOS devices. This leads to increased delays and timing failure. The impact of NBTI is higher in advanced nodes. In addition, the impact of NBTI increases as VDD decreases, which is a common trend in advanced nodes to reduce power.”

Understanding NBTI
Negative-bias temperature instability is a degradation mechanism that affects PMOS transistors. It stems from changes at the at the interface between the gate oxide and the channel. The result can be anything from an increase in threshold voltage and leakage current to a reduction in mobility, drain current and transconductance.

“NBTI has become more important as a result of process scaling,” said Art Schaldenbrand, senior product manager at Cadence. “Process scaling results in increased electric fields across gate oxides. Devices operate at higher temperatures due to higher power dissipation and more complex gate oxide stacks. And all these factors contribute increased susceptibility to NBTI. As scaling has continued down, n-channel transistors are also beginning to show susceptibility to positive bias temperature instability (PBTI).”

But NBTI is also hard to predict. “Making analysis of the problem even more complicated is that, depending on how the device is operated/stressed, the device can recover from the BTI effect,” said Schaldenbrand. “Since NBTI increases threshold voltage and reduces mobility, it impacts timing, dynamic power, leakage circuits of digital standard cells.”

Electromagnetic (EM) coupling only complicates the problem. It can result in very large delay variations, depending on the switching conditions of a large set of coupled signals.

“These delay variations decrease timing margins significantly, and hence tolerance to NBTI aging effects is less and failures can happen earlier,” said Helic’s Abadir. “Magnetic coupling, unlike capacitive coupling, is very far reaching and is hard to shield against. As a result, more delay variations can occur due to magnetic coupling as compared with capacitive coupling. These magnetic coupling induced variations also affect clock jitter and worst-case skew, further exacerbating the timing margins crunch. The margin for NBTI tolerance is subsequently significantly reduced due to electromagnetic coupling.”

Also, magnetic coupling and inherent inductance effects in the power distribution network (PDN) results in droops in the PDN, decreasing the effective value of the supply to a CMOS gate. With decreased supply, NBTI effects are known to increase, he said.

Magnetic coupling is known to cause overshoots and undershoots in a signal, which can be significant in the worst-case switching conditions when signals switch in the same direction creating an additive magnetic field, according to Professor Yehea Ismail of the American University of Cairo.

“These overshoots and undershoots can easily exacerbate NBTI effects through several mechanisms,” Ismail said. “The overshoots result in high electric fields that can cause hot electron effects changing the threshold voltage in a way that adds to the NBTI effect significantly. In addition, these signal fluctuations around VDD at the input of a gate results in an effective value of a ‘1’ other than VDD and change the effects of NBTI. Furthermore, overshoots result in bi-directional currents in the PMOS transistors beyond the typical uni-directional CMOS current that is needed to charge the output capacitance to VDD, resulting in excess heating in the PMOS transistors and increased NBTI.”

Improving reliability
Accordingly, increasing design reliability can be achieved in a number of ways, said Ismail. “First, properly modeling physical properties of the design (e.g., RLCK extraction) and incorporating these accurate models in calculating the key performance metrics of the design (delay, effective VDD, power consumption, coupling noise, etc.) instead of the common practice of using simple models and then relying on arbitrary and costly margins. Note that if there are several sources of variations that are not being modeled accurately, the use of some arbitrary margin will not address key design issues and can be extremely costly.”

In addition, design reliability can also be increased by using appropriate aging models to estimate the expected age of the devices under real usage and environmental conditions, he added.

Arm’s Dodrill suggested that the simplest way to account for transistor aging at the SoC level is to include additional timing margin for setup and hold. “A slightly more sophisticated way to account for it would be to set the critical range to at least 10% of the clock period for setup and include additional timing margin for hold paths that include gated clocks. Characterization of IP to include the effects of aging, like NBTI, are not very useful without a path level STA solution. The ultimate solution is EDA software that takes aging into account when performing static timing analysis, which is no small task; each transistor has a unique switching context. Additional characterization, modeling and analysis will add to the already CPU-intensive design and validation of IP and designs, but it is required if we are to properly account for the effects of NBTI without adding overly pessimistic margins.”

Advanced NBTI models, including NBTI variability, are being developed and made available to circuit designers, noted Fraunhofer’s Giering. Unlike traditional empirical NBTI models, advanced models exploit physical insights to permit high-accuracy predictions of NBTI aging.

Even with some technology in use, Ahmed Ramadan, senior product engineering manager for the AMS Foundry Program at Mentor, a Siemens Business, said NBTI is one of the most important threats for MOSFET devices—whether NMOS or PMOS—in VLSI circuits today. “As the electrical stress on a transistor increases, there are issues related to the silicon die-side interface. With the high amount of stress and the high temperature that is applied on this interface, traps will be generated inside the oxide, causing the gradual wearing out of a device. It’s a gradual wear-out. It’s not a sudden wear-out that can happen under the original testing of the device and accordingly. That’s why it’s dangerous. You cannot get out of it instantaneously when the device is under stress.”

It only gets worse from there. “Eventually, all circuits will fail because as transistors become slower,” said Ramadan. “There are also issues regarding mismatch between two devices. You can have one device that has degraded more than the other, which can be part of something like a differential pair, so they are not matched anymore. And one of the traps that can happen in a circuit is that the leakage current can become greater.”

Predicting recovery from NBTI isn’t simple, either. “To predict that recovery, it’s necessary to have a good dynamic model that can be used in simulation and that can account for this recovery effect,” he said. “When we are talking about advanced technology nodes, you’ll find integrated circuits are working for a longer time than they previously were, which can cause the chip temperature to increase over time.”

Higher temperatures have an effect on NBTI. So do ultra-thin gate oxides.

“A lot of devices in advanced technology nodes use ultra-thin oxide for the gates, and techniques to mitigate the use of ultra-thin oxide can cause leakage,” said Ramadan. “To resolve this leakage problem, high-k dielectrics plus metal gates are used. If you use high-k dielectrics, that means that you can introduce more silicon dioxide interface traps. Those, in turn, can create a higher probability for degradation because of something like NBTI. This is why it’s more much more significant in advanced technology nodes where thin oxides using high-k dielectrics are used.”

Fig. 1: Reliability bathtub curve. Source: Wikipedia/Wyatts derivative work

Toward more standards
It doesn’t help that each EDA tool provider today uses its own proprietary model to do recovery prediction, but progress is happening there, as well.

“There are no standard models that are in place today,” Ramadan said. “EDA vendors have each developed models for that. But industrywide, foundries are developing their models, institutions are developing their models, so a lot of effort is currently happening by standardization committees including the Compact Model Coalition (CMC) to develop a standard model for aging that not only targets NBTI but also hot carrier injection, TDDB (time-dependent gate oxide breakdown) and any other degradation mechanism. This is a collaborative effort between different companies, including foundries, EDA vendors, IDMs, and educational institutes such as the University of California at Berkeley, Hiroshima University, and others.”

Again, as reliability simulation and aging grows in importance with advanced nodes, NBTI is a key part of design and manufacturing that must be addressed.

On the foundry side, some semiconductor manufacturers may handle everything from providing and tuning the models to their technology. These models may be physical models, or partially physical, and partially empirical to match the technology. Some foundries even develop their own aging interface that can be used in running circuit simulation across each of the EDA vendor solutions today.

This aging interface is necessary to run aging simulation, and today each of the largest EDA tools providers has its own solution for aging. There is growing concern that the foundries may not want to continue supporting all of these solutions, and as a result, the CMC has been working for the past seven years on developing a standard aging interface, the open model interface (OMI). This is simulator agnostic, so if it is supported by any of the EDA vendor tools from different EDA providers, it can provide them a single interface that can be used by the foundries. All they need to do is to develop their own model, place it inside the interface and it should be working across different EDA vendors.

Proponents suggest this would also free customers to not be reliant on a single solution from a single EDA vendor. Instead of focusing on the interface itself, industry efforts could be addressing how accurately the models represent the technology that’s needed by the industry and customers today.

Until the standards discussion is worked out, multiple parties will forge ahead to improve device reliability by addressing aging and NBTI in whatever way they can.


David Leary says:

Ann, it’s very difficult to find parameters (gamma and Ea) for bias life testing (HTOL) reliability modeling for BTI Vt instability. For such modeling for FinFET silicon, I see Ea ranging from 0.4 to 0.53 eV, and gamma ranging from 6 to 15 V-1. Can you comment on what you are finding is industry standard for FinFET silicon?

Narek Shukhyan says:

That’s a very interesting article.
I guess if there is an article regarding Wafer Level Reliability and it’s testing challanges on your website.

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