Process Corner Explosion

At 7nm and below, modeling what will actually show up in silicon is a lot more complicated.

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The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal.

Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what is actually going to show up in silicon, and it provides guidance to the design team. But that guidance is getting far more difficult to follow.

“The foundry doesn’t produce exact copies of transistors or chips,” said João Geada, chief technologist at ANSYS. “It’s not an exact process. There’s some random variability. To a certain extent that’s kind of hard to deal with from an engineering point of view. Process corners are, in a way, an attempt to put the bound on what comes out of the foundry—what’s the fastest something can happen, what’s the slowest, what’s the worst power, what’s the least power? There are multiple dimensions that you need to take into account, but you’re trying to basically put a box around what will come out the foundry; the corners are the edges of that box.”

While that seems straightforward, the problem is the number of dimensions of this box, Geada said. “Dealing with just the transistors, there’s n versus p. The typical scatterplots that people talk about when they talk about process are usually some characteristic of n transistors, plotted against some other characteristic of p transistors. This is captured in the overall scatterplots you typically see when you’re talking about processes, and process corners.”

Typical Corners:
• FF (fast fast)
• SF (slow fast)
• SS (slow slow)
• FS (fast slow)
• TT (typical typical)

To complicate matters, there isn’t just one set of parameters that need to be looked at.

“Typically people talk about speed, and the ability of the transistor to supply current, but we also care about the behavior of leakage currents,” he said. “We care about threshold voltages. Those have their own scatterplots, and these plots are not independent of each other. In addition, the shape of these scatterplots changes with temperature and voltage, so this is where the number of corners that you have to deal with at the design level starts climbing up because the shape of the box, and the dimensions of that box changes at different operating environments.”

The design team may be more concerned with certain aspects of corners, and those might be different from one design to the next. For instance, ultra-low-power chips may have different tradeoffs than high-performance chips, and this is where things get complicated.

“Certain types of designs, like the chips we put in mobile phones, care about all dimensions because they run in high performance mode when you’re playing a game or doing something intensive on the phone,” Geada noted. “But when it is just sitting idle, you want it operational and still functional, but at the lowest power point. So they have to be optimized in a bigger set of profiles.”

For high-performance designs, the goal is a combination of speed and the lowest possible power.

“Designers will design around a corner,” said Magdy Abadir, vice president of marketing at Helic. “They pick a corner that’s a little bit away from the very worst case, because that’s very pessimistic and would not allow them to get anywhere with the performance goals they’re trying to achieve. They will design it around something in the middle or slightly aggressive, do their timing analysis, do the power analysis, do everything. In this way, the bulk of the design activities are done around the corner. Then, once they reach a final answer like the design layout is there, the design meets timing, etc., these designs typically will have a margin of error.”

The size of that error can vary. “When the foundry refers to the timing goal, it means you need to hit the timing of the paths within 10% of, let’s say, the actual number,” Abadir said. “There is about 10% or 15% slack, depending on the maturity of the process, depending on things like how much yield they are hoping to get. In the final month or two of tapeout, the design team will start running the higher end corners that are very aggressive to see if these corners will take what they designed. They take the same design that they had, run the extraction against this worst case corner. They will also re-do the timing, re-do the power calculation, and see what happens to these numbers. If it’s way off, they start working on which ones are causing the problem and may tweak them. They try to do as much as they can in the last couple of months. It’s a matter of positioning and allowing a little bit of margin to see how far they are if the worst case conditions from the process variations happen, but it is a very non-scientific endeavor.”

Nevertheless, it’s also an essential endeavor. “We need to ensure our designs are manufacturable and demonstrate the required performance across manufacturing variability of advanced node processes,” said Sunil Bhardwaj, senior director of business operations for IP cores at Rambus. “To do this, we perform design simulations using process corners representing the process manufacturing variability on both transistors as well as metal backend. We combine process FET corner combinations with parasitic RC corners, along with variability on voltage and temperature, to ensure design robustness. As an example, a SS (slow nMOS and slow pMOS) process corner is simulated along with a maxRC (maximum resistance and capacitance) parasitic corner and an FF (fast nMOS and fast pMOS) process corner is simulated with a minRC (minimum resistance and capacitance) parasitic corner. Since the design is mixed signal, it also contains multiple voltage supply domains, which we also need to account for and simulate multiple supply domain corners. For example, a typical 2-power-supply design will run 30+ corners.”

Metal changes, too
There’s another catch, namely changes to metal. “Metal is actually a little bit different in that there can be anywhere between nine to tens of metal tracks, and each metal track varies differently from the next one,” Geada said. “They are very well correlated on a per-layer basis, but they are not all that well correlated between layers. There are also different characteristics of metal, and typically with metal extraction you are extracting for maximum resistance, minimum resistance, maximum capacitance, minimum capacitance or also frequently min or max RC product. These are all of the various individual scatterplots you can get, so when you’re designing a chip and trying to maximize how much yield you are going to get and how well they are going to work, you need to figure out where your design fits within all of these process spaces. This is when the corner explosion comes up, because you have to look, particularly for sign-off. There’s the design corners and then there are the sign-off corners, which is why it’s really hard to get the straight answer of how many corners you need.”

Some of this is a judgment call. “You start avoiding some of these things in the design of the buses, or long wires on the circuit, but clocking is a very important factor,” said Abadir. “Things like EM (electromagnetic) coupling are not a problem because this is not modeled. There aren’t many designs that even model it. They don’t model inductance so this is the unknown factor. Smart designers may say that since it’s not going to affect these layers, they are okay. ‘It’s not going to affect me in this area. But in this other area, let me do the analysis, let me worry about this, something here and there.’ So it’s still an art. It is not really science in the same sense of saying, ‘Here is an algorithm that is guaranteed to work even with oldest dates about process variation.’”

This is true no matter how well various components and IP are characterized. “Even if you have all the characterization in the world, you cannot characterize for everything,” Abadir noted. “If I go too pessimistic I’m not going to be competitive. And if I go too optimistic, it will have zero yield and I would never hit my target. It relies on a lot of experience. Companies that have been designing certain classes of designs have this experience. They have experienced designers that know what to do and what not to do and how much you should push on the gas here and you should take off your foot on the gas there.”

So how many corners should be run? There’s no clear answer to that question.

“It depends,” said Steven Lewis, marketing director at Cadence. “You may have to run some in min, some in max, then reverse those, then run some at typ, some at max, reverse those, and so on. If you had four different processes that you were running, and you had three different corners for each of the processes across three different voltages and across three different temperatures, and you need to do all of the different combinations, you start to stack up a lot of simulations that need to be run. And that’s the bare minimum. There are design teams working at advanced nodes that don’t just have min, typ, max; they may have six or seven different corners that they need to check. They may have a corner that’s at the extreme tail, they may have corners that are at the three sigma portion because they want to encapsulate a lot of the circuits behavior. Of course they’ve got some corners at typical, but maybe they want to do a little bit more testing. They might have a few different corners around the typical mean range. So now when you’re multiplying corners against each other, it’s a multiplicative problem. It’s these transistors’ corners multiplied by those transistors’ corners multiplied by that transistors’ multiplied by the temperature multiplied by the process voltages. Before long, you’re up to what some of our customers do, where they will check anywhere from 800 to 1,100 different corner combinations.”

Typically within a digital design flow, there are four corners to be taken into account for the MOSFET devices—worst speed, worst power, worst one, and worst zero. That’s just the starting point.

“The standard cells are characterized for those typical corner cases,” said Torsten Reich, group leader for integrated sensor electronics at Fraunhofer EAS. “This gets combined with other parameters such as temperature or VDD, which yields at least 16 corners. Using techniques such as power or frequency scaling further increases the number of corners. It is a different story for analog, where even the standard technologies are more complex, since in addition to the MOSFETs we have corners for the resistors, caps and bipolar devices. This yields at least 32 corners, which also gets multiplied by the number of temperature and VDD corners. On top of that we need to care for the variability of the external voltage reference. In total this leads to about 200 PVT corners in the verification flow. For advanced nodes, even the digital flow becomes increasingly complex regarding the corners to be checked. In FD-SOI processes, for example, transistors can be operated either in high performance or in low leakage configuration, which is controlled by the backgate voltage. Digital cells need to be characterized over the backgate voltages in addition to the usual parameters, which again increases the number of corners to be checked during verification.”

Still, there is a lot of work happening in advanced nodes especially, 7 and 5nm, observed Shekhar Kapoor, director of marketing at Synopsys. “Process corners are only one part of the equation. The traditional number of process corners hasn’t really changed, along with the RC corners. The challenge really has been variation effects. The local/on-chip/on-die variation part, has really become the biggest challenge. The days of doing flat global margining, which brings in a lot of pessimism and overdesign—that’s the problem that everybody is talking about.”

Kapoor noted that foundries went from five traditional corners to so-called global corners. “Not all foundries do that, but some of them do the global fast, fast and global slow, slow, which has included some of these on-die or local variations in there. The industry-wide work is continuing in that vein. There are ultra-low-voltage operations, which are really making it even more problematic. You have to ensure the proper operational and functioning at 0.4 volts and even below. We’ve been working with foundries to address that. One part is, with POCV (parametric on-circuit variation), how do you continue to extend that?”

Again, what makes dealing with process corners so challenging is that for a typical process node there are 3 to 6 device corners, 5 to 11 interconnect corners, and then several corners for temperature and voltage, noted Carey Robertson, product marketing director at Mentor, a Siemens Business. “These have a multiplicative effect, which means if you have 3 device corners, 5 interconnect corners, 2 temperature and 2 voltage. You need to do 3 x 5 x 2 x 2 = 60 simulations for complete coverage.”

To achieve this, the design team needs to generate the 60 circuit ‘views’ or netlists that represent each corner, and then they have to do the actual simulation, Robertson explained. “Dealing with the time and compute resources required is daunting. Second, understanding what is truly important is a difficult consideration. Do you have to close your design across all corners or are some corners more important than others? Statistically speaking, what are the most important corners to focus on?”

To make it easier for EDA companies to make better tools in this area, foundries could provide better statistics to help EDA tools and customers prioritize better, Robertson suggested. “With better data we may be able to provide better guidance so a designer is not trying to optimize for a ‘slow’ device corner with a ‘fast’ interconnect corner, for instance.”

Currently, there are tools that will enable concurrent generation of the circuit netlists (or views) so that a user does not have to explicitly invoke the tool multiple times to get different netlists. On top of that, simulation tools are improving to do faster analysis (with better techniques and multi-CPU), as well as helping customers identify what are the sensitive circuits that will be impacted due to corner variation. That allows designers to focus on where they will improve the circuit the most.

Advanced challenges for leading edge
Indeed, advanced nodes such as 7nm and below have made it that much more challenging to account for the corners in a design. “For interconnect corners, there was a large increase with the advent of multi-patterning,” Robertson said. “With multi-patterning, you know have geometries on the same layer represented in different masks, which means not only is there inter-layer variation (as has always been the case), but you know have intra-layer variation due to mask shifts. Anytime you introduce more processing steps or add layers there is an opportunity for variation that needs to be captured in a model or, potentially, in the description of another corner.”

And with today’s design and process complexities, designers need to keep in mind that worse-case conditions for any circuit depends on the specific circuit, and can be different depending on what metrics are used to evaluate. “For example, for the worse case power conditions, in some cases slow process corner could result in higher power depending upon parasitic loading effects. Multi-supply circuits require simulating skewed supply corners and understanding impact on leakage paths,” Rambus’ Bhardwaj said.

In the case of mixed-signal designs, the simulation corners used in analog design can be matched to the corners in digital design to get the worst-case timing analysis. “Designers work hard to create robust designs, verifying performance across all corners while ensuring that power/area targets are achieved—tighter process corners go a long way to enable designers to do this successfully,” Bhardwaj said. “Additionally, product robustness is especially critical to solving network application needs, that include high reliability over a long lifecycle.”

At the end of the day, dealing with process corners is a bit like the weather. “The most reliable way of predicting today’s weather is exactly the same as it was yesterday,” said ANSYS’ Geada. “The same thing is true with process corners. Whatever worked last time is probably, with small tweaks, the same thing that will work this time unless — and this is where things get scary for most people — something has happened in the process that no longer behaves the way it used to. This is why people are suddenly getting really concerned at 7nm and below, because a whole bunch of effects that people thought would be coupled suddenly aren’t. This is why suddenly you’re hearing a lot about timing-voltage interactions, because at small voltages and at these processes these two parameters that were being optimized independently could no longer be treated independently.”

Sometimes the design space changes, too, such as adding reliability into automotive chips.

“Not only how does it work today, but how is it going to work 10 years from now,” Geada said. “All of a sudden you’ve now opened a dimension in your process space that we didn’t use to look at.”



1 comments

Bill Martin says:

Given how variation’s affect continues to increase with smaller geometries (as expected), it’s about time that many designs stop chasing ever denser homogeneous silicon using latest silicon nodes. Years ago the adage was “real companies own silicon fabs”. This was replaced by the disaggregation of this model by “fabless” companies. But these companies still chased and used the latest silicon technologies for cost, speed and power. Adage: “Real companies design silicon”.

Another inflection is happening where many fabless will NOT see the benefits of chasing sub 10nm silicon. The costs (time, engineers, SW tools, NRE) and RISKS will be to great. A good percentage of fabless will remain at higher nodes and a splinter sect of companies will start to use (or create their own) platforms based on small systems similar to Arduino or Raspberry Pi that provide significant processing/functional capabilities in a pre packaged and tested “LEGO block” approach easily connected by std interfaces only requiring application programming. The nextgen company’s adage: “smart companies used pre designed, manufactured and tested processing platforms to reduce time and cost to develop”.

This will have an interesting impact on the EDA ecosystem: the lower end tools being eliminated by these super plug&play modules while the higher end, costly tools have a smaller SAM.

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