GAA NSFETs: ML for Device and Circuit Modeling

A new technical paper titled "A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors" was published by researchers at National Yang Ming Chiao Tung University. Abstract (excerpt) "Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domai... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs

A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs

A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich. Abstract: "Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the co... » read more

Large-Scale Integration’s Future Depends On Modeling

VLSI is a term that conjures up images of a college textbook, but some of the concepts included in very large-scale integration remain relevant and continue to evolve, while others have fallen by the wayside. The portion of VLSI that remains most relevant for semiconductor industry is "integration," which is pushing well beyond the edges of a monolithic planar chip. But that expansion also i... » read more

Improving Performance And Lowering Power In Automotive

Automotive OEMs are boosting their investments across the semiconductor ecosystem as stepping stones toward electrification and autonomy, and they are starting to encounter some of the same issues chipmakers have been wrestling with at advanced nodes — massive compute performance, thermal and power issues, reliability over extended lifetimes, and a highly diverse and geographically distribute... » read more

Balancing AI And Engineering Expertise In The Fab

Modeling and simulation are playing increasingly critical roles in chip development due to tighter process specs, shrinking process windows, and fierce competition to bring technologies to market first. Before a new device makes it to high-volume manufacturing, there are countless engineering hours spent on developing the lithography, etching, deposition, CMP, and many other processes, at hi... » read more

True 3D-IC Problems

Placing logic on logic may sound like a small step, but several problems must be overcome to make it a reality. True 3D involves wafers stacked on top of each other in a highly integrated manner. This is very different from 2.5D integration, where logic is placed side-by-side, connected by an interposer. And there are some intermediate solutions today where significant memory is stacked on l... » read more

Impact Of Increased IC Performance On Memory

Increasing performance in advanced semiconductors is becoming more difficult as chips become more complex. There are more physical effects to contend with, different use cases, and challenges in making memory go faster. In addition, aging effects that once were ignored are now becoming critical concerns. Steven Woo, fellow and distinguished inventor at Rambus, talks about different factors that... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Design And Verification Methodologies Breaking Down

Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

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