tag: voltage

Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung)
By Technical Paper Link - 25 May, 2026 - Comments: 0

A new technical paper, "Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory," was published by researchers from University of Seoul and Samsung Electronics. Abstract "This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggres... » read more

Doping-Dependent Charge Trapping in WS2 FETs (KU Leuven, imec, TU Wien)
By Technical Paper Link - 12 Jan, 2026 - Comments: 0

A new technical paper titled "Impact of doping and channel inhomogeneities on the stability of industrially fabricated WS2 FETs" was published by researchers at KU Leuven, imec and TU Wien. Abstract "We report doping-dependent charge trapping in WS2 field-effect transistors fabricated on a 300 mm wafer. In particular, higher n-type doping–associated with smaller channel areas–correlat... » read more

Energy-Efficient Signal Detectors For Massive MIMO Using SRAM-Based IMCs (Univ. of Illinois at Urbana–Champaign)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing" was published by researchers at the University of Illinois at Urbana–Champaign. Abstract "This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input mu... » read more

Heat-Related Issues Impact Reliability In Advanced IC Designs
By Ann Mutschler - 18 Jul, 2024 - Comments: 1

Heat is becoming a much bigger problem in advanced-node chips and packages, causing critical electrons to leak out of DRAM, timing and reliability issues in 3D-ICs, and accelerated aging that are unique to different workloads. All types of circuitry are vulnerable to thermal effects. It can slow the movement of the electrons through wires, cause electromigration that shortens the lifespan of... » read more

Staying Within The Margins
By Barry Pangrle - 28 Mar, 2024 - Comments: 0

Last March I wrote an article called Squeezing the Margins that’s about a design that used an adaptive clocking scheme to keep the performance of a system high while simultaneously keeping the temperature below a specified maximum. Last August we looked at Managing Voltage Variation and how an adaptive clocking scheme could be used to manage dynamic voltage drop to maximize system performance... » read more

What Data Center Chipmakers Can Learn From Automotive
By Anne Meixner - 11 Apr, 2023 - Comments: 2

Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

Antiferroelectric negative capacitance from a structural phase transition in zirconia
By Technical Paper Link - 12 Apr, 2022 - Comments: 0

New research paper from 24-person research team from Berkeley, Georgia Tech, MIT, and other institutions. Abstract "Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectrici... » read more

Optimizing Power Supply
By Cadence - 10 Feb, 2021 - Comments: 0

Any electrical engineer knows providing power to your board is a key feature in PCB design. While most boards can be functional, their true quality shines when the perfect level of power to components is achieved. Building and designing better power supplies is the best way to ensure the end-product has full life-cycle potential. But how do we ensure we can convert a (potentially variable) i... » read more

Where Timing And Voltage Intersect
By Ed Sperling - 14 Feb, 2020 - Comments: 0

João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

Non-Volatile Memory Tradeoffs Intensify
By Ann Mutschler - 22 Jan, 2020 - Comments: 0

Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the ... » read more

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