Staying Within The Margins

Last March I wrote an article called Squeezing the Margins that’s about a design that used an adaptive clocking scheme to keep the performance of a system high while simultaneously keeping the temperature below a specified maximum. Last August we looked at Managing Voltage Variation and how an adaptive clocking scheme could be used to manage dynamic voltage drop to maximize system performance. This article looks at a scheme based on measuring change in the timing of the circuits to keep performance at a maximum while not violating timing constraints.

Figure 1 below shows a simple example logic path between two clocked registers. For the circuit to function correctly, there must be enough time during one clock period for the new output to appear at the input register and then that signal to enter the logic and have the logic produce a good stable value and have it appear to meet the setup time of the second (output) register and the good stable value be maintained for the necessary hold-time so that it’s properly captured by that register.

Fig. 1: Example Logic path between two clocked registers

Any changes in the voltage or temperature can impact the speed of the logic path and registers. Typically, an increase in voltage will speed up the circuit and a decrease in voltage will slow it down. The effects of changes in temperature are a little trickier with the many FinFET devices as the voltage level impacts whether a change in temperature will speed up or slow down the circuit. Obviously, if the voltage and temperature slow down the circuit it’s at risk of failing to meet timing which will cause incorrect behavior.

One approach for managing this is to provide separate voltage and temperature sensors and then calculate based on the combination of the two whether the circuit is still within its safe correct timing envelope or whether the clock should be adjusted lower to meet the new slower timing. Of course, each sensor will have its own accuracy limits and having multiple sensors means that there’s a multiplicative factor in terms of the errors of the combined sensors. Another factor is any clock uncertainties, for example jitter which can cause consecutive clock periods to be slightly shorter or longer than the target clock frequency. Typically, this is margined into the calculation to keep the circuit within normal working parameters.

What if we had a sensor though that could act as a proxy for the timing and have it automatically take into account changes in process, voltage, temperature and clock variation? If the real goal is to keep the circuit running within an environment where timing is always met then such a sensor could also be used in an adaptive clocking system where any time it detected that the margin was getting too close to a failure mode, the clock could automatically be adjusted lower as needed.

To provide some insight into how such a sensor could work, we’re going to use an analogy with a sports car that’s being timed, and the distance travelled during that time is what’s being recorded. (Think 24 Hours of Le Mans, except it’s a really short nano or sub-nano second race.)

Fig. 2: Fixed time, measured distance

Figure 2 shows an example where our car is at the starting line at t=0 and then at t=finish we record how far the car made it down the course.  The car that travels the farthest in the fixed time interval has the highest average velocity. So how does this correlate with our proposed timed delay line sensor? Figure 3 below shows an annotated version of Figure 2.

Fig. 3: Annotated fixed time, measured distance

Here we equate our sports car with a pulse edge that is racing down a delay line. We’ll use a fixed frequency clock to set the timing interval.  The higher the voltage, the farther the pulse will travel down the delay line and the “distance” value will be captured as a digital indicator of the available margin. The higher the value, the more margin that’s available.

If we hold the voltage and temperature constant across different pieces of silicon, we can gain useful information about the process point. If we capture the value for a “typical-typical” chip then values captured for other chips that are below or above our known value would indicate slow or fast silicon respectively.  As the chip ages, any timing variation would automatically show up.  For clock variation such as jitter, if the clock period is shorter, it’s like stopping our stopwatch early and it’s a real reduction in margin and it will also show in the captured value.

Having real-time values available also opens the possibility for performing many forms of analysis, including creating predictive algorithms to stay a step ahead of any possible upcoming future variations in voltage and/or temperature.