The Challenge Of Defining Worst Case


Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

Curvilinear Full-Chip ILT


Leo Pang, chief product officer and executive vice president at D2S, talks about the speed improvements with full-chip inverse lithography technology, why it is so critical in stitching together large chips, and how this approach differs from traditional litho approaches. » read more

Monitoring Heat On AI Chips


Stephen Crosher, CEO of Moortec, talks about monitoring temperature differences on-chip in AI chips and how to make the most of the power that can be delivered to a device and why accuracy is so critical. » read more

Less Margin, More Respins, And New Markets


Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Why Chips Are Getting Noisier


In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Low Power Meets Variability At 7/5nm


Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Multi-Physics At 5/3nm


Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

New Design Approaches At 7/5nm


The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge manufacturing processes are involved. There are two fundamental problems. First, there are much tighter tolerances for all of the components in those designs due to proximity effects. Second, as a re... » read more

Thermal Guard-Banding


Stephen Crosher, CEO of Moortec, talks with Semiconductor Engineering about the impact of more accurate measurements on power, performance and reliability of designs from 40nm all the way down to 3nm. https://youtu.be/VnX-TiaMVmI » read more

Inferencing In Hardware


Cheng Wang, senior vice president of engineering at Flex Logix, examines shifting neural network models, how many multiply-accumulates are needed for different applications, and why programmable neural inferencing will be required for years to come. https://youtu.be/jb7qYU2nhoo         See other tech talk videos here. » read more

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