Multi-Physics At 5/3nm


Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

Power Issues Grow For Cloud Chips


Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

Temperature Reduction on a High-Power Thermal Demonstrator


High-power applications in microelectronic devices and systems is a crucial and severe issue that may cause elevated thermal and thermomechanical phenomena and finally lead the fabricated system to degradation, limitation of its performance, or even failure and destruction of its features. In specific applications, such as those found in the industry and the automotive sector, the power pro... » read more

Aging Effects


Tech Talk: Fraunhofer EAS' group manager for quality and reliability, Andre Lange, talks about how to model aging effects and why the problems are becoming more difficult at advanced nodes. https://youtu.be/XHWww2PE7aY » read more