tag: PVT

Addressing SRAM Verification Challenges
By Siemens EDA - 26 Oct, 2022 - Comments: 0

SureCore Limited is an SRAM IP company based in Sheffield, the United Kingdom, that develops low power memories for current and next generation silicon process technologies. Its award-winning, world-leading, low power SRAM designs are process independent and variability tolerant, making them suitable for a wide range of technology nodes. Two major product families have been announced: PowerM... » read more

Enabling SoC Visibility For Future Secure Hardware Architectures With In-Chip Environmental Monitoring
By Ramsay Allen - 07 Jun, 2022 - Comments: 0

Billions of people around the world are now online and generating vast amounts of data every day. This data revolution, which is largely driven by user performance requirements, is a double-edged sword. On one hand it is enabling huge technology advancements, revolutionizing the way we connect with each other and the world around us, but on the other hand it is exposing major vulnerabilities in... » read more

Adding Circuit Aging To Variability
By Brian Bailey - 12 Aug, 2021 - Comments: 0

Moving to a smaller node usually means another factor becomes important. The industry has become accustomed to doing process, temperature, voltage (PVT) corner analysis, but now it has to add aging into that mix. The problem is that planning for circuit aging is no longer a purely statistical process. Aging is dependent on activity over the lifetime of the device. Tools need to be modified a... » read more

Best 112G SerDes IP Architecture
By Manu Verma - 08 Jul, 2021 - Comments: 0

Real world operation of a serializer/deserializer (SerDes) in a hyperscale data center is very demanding and requires robust performance in challenging conditions such as multitude of channel insertion loss, extreme temperature cycles, different types of packages with different trace lengths and discontinuities, etc. Hence, meeting interference tolerance (ITOL) and jitter tolerance (JTOL) compl... » read more

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy
By Ramsay Allen - 11 May, 2021 - Comments: 0

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Next-Gen Design Challenges
By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Wrestling With Variation In Advanced Node Designs
By Ann Mutschler - 19 Feb, 2020 - Comments: 5

Variation is becoming a major headache at advanced nodes, and issues that used to be dealt with in the fab now must be dealt with on the design side, as well. What is fundamentally changing is that margin, which has long been used as a buffer for variation and other manufacturing process-related problems, no longer works in these leading-edge designs for a couple of reasons. First, margin im... » read more

Less Margin, More Respins, And New Markets
By Ed Sperling - 10 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Multi-Physics At 5/3nm
By Ed Sperling - 11 Apr, 2019 - Comments: 0

Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

Power Issues Grow For Cloud Chips
By Ann Mutschler - 11 Oct, 2018 - Comments: 0

Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

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