In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product?

Advanced node and finFET design challenges

There are three main challenges associated with advanced node and finFET designs:

1. There are challenges associated with transistor scaling, where gate density is increasing dramatically for each generation of finFET node, leading to power distribution, dissipation and resulting thermal challenges.
2. Complexity within the chips themselves, with increasingly higher levels of interconnect and available routable metal layers.
3. There are challenges associated with the intricacies of modern systems.

On this last point we see the emergence of chiplets, 2.5D, and 3D multi-chip module arrangements has meant differing silicon is being used in a single packaged system, compounding the already pronounced issues of complexity, increasing the potential risk of defects, and further raising the topic of chip, product, or system reliability and resilience. Layering into these challenges is the observation that chips operating in the field are impacted by the level of dynamic activity, often difficult to determine as execution software evolves and is upgraded over time. Insurance is guarding against all possible eventualities, however, with these advanced node challenges, we’re facing certain eventualities.

Why this sudden evolution of embedded monitoring?

Gone are the days where the application of in-chip Process, Voltage, and Temperature (PVT) monitoring was simply a precautionary measure. As we seek more reliable and more compelling products across data center, AI, automotive, and consumer applications, these new challenges for design, manufacture, test, and in-field deployment of silicon demands a paradigm shift in our thinking. Simply put, we need greater visibility from within the chip.

Monitors are now critical to achieving successful functional operation and compelling performance of our latest semiconductor technologies. That these are new, immature processes yet to be seen at high wafer volumes also means monitors need to tell us what the lifetime aging and degradation impacts will be on circuit performance. To be insightful, we need a combination of embedded data sources together with analytics that is able to take a view across entire product ranges, allowing us to determine trends for power consumption, device speed, and assist us with assessments of longevity, leading us to revolutionary concepts of predicting when product maintenance is required and also when its ultimate demise will occur.

More than traditional PVT sensors

Looking at the staple line-up of process, voltage and temperature sensors that has thus far enabled all finFET based products, we can start to see what’s coming next in the evolution of in-chip sensor technologies. Process monitoring, once solely placed within scribe lanes, has pushed its way in to the chip’s core, now allowing localized process speed assessment to measure of not just die to die but also on chip variation across individual die. Extensions of process monitoring will enable design margins to be measured, allowing dynamic scaling schemes to push supply levels and data throughputs to even more optimal levels.

In a wider respect, the future of sensor development will understand the dynamic conditions in a more accurate, distributed, and granular way to manage power effectively. In play already is real-time assessment and control of circuit activity on a per CPU core level, allowing workloads to be distributed evenly. With respect to silicon aging, degradation, and demise, we continue to evolve toward continuous testing and self-analysis supported by sensors able to expose anomalies, enabling further clarity to the root cause analysis of failure.

Trusting the insurance salesman

So, we’ve managed to create a compelling argument for sensor adoption into our cutting-edge process designs, but how much can we trust the sensor data generated? After all, we’re making big decisions about on-chip power management, chip protection, and reliability based on ‘sensor-speak.’ To help ensure the integrity of the measurement information generated, we start to see the health status of the sensors themselves being reported. So now a failing embedded thermal sensor can inform the system to switch to ‘safe-mode,’ producing meaningful benefits to safety-critical applications such as automotive. Furthermore, sensor solutions that cater for potential catastrophic failure are now available, providing low-latency alert conditions directly to the system. One example is the thermal catastrophic protection circuit (see figure 1) that alerts the system to sudden device thermal runaway situations.

Fig. 1: Thermal catastrophic protection circuit.

From my own experience, once upon a time, embedded sensor conversations with chip architects and designers used to start with the same cynicism usually applied to an approaching insurance salesman. However, with the industry understanding the critical nature and the benefits that silicon lifecycle management and analytics can bring to bear, I’m now seen more as an enabler to compelling silicon product.

Synopsys offers a complete fabric of embedded in-chip sensors and PVT monitors from 28nm down to 3nm, configurable by application for data center, AI, automotive, 5G, and consumer. The IP is available as part of the DesignWare foundation IP portfolio and also forms the basis of the Synopsys Silicon Lifecycle Management (SLM) platform. Further information can be found at www.synopsys.com/SLM.