tag: finFET

Understanding Why Drain-Current in GAAFETs Deviates from Thermionic Dependence at Negative Gate Voltages (Sandia National Lab, LIST)
By Technical Paper Link - 05 May, 2026 - Comments: 0

A new technical paper, "Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors," was published by researchers at Sandia National Laboratories and Luxembourg Institute of Science and Technology. Abstract "Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect tra... » read more

Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance
By PDF Solutions - 10 Feb, 2026 - Comments: 0

Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. The presented study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7nm FinFET transistors. Variations in critical dimension ... » read more

Examining Mechanical Deformation In Advanced Logic Devices To Enhance Yield
By Sandy Wen - 19 Jun, 2025 - Comments: 0

By Sandy Wen and Jacky Huang As dimensions shrink and aspect ratios increase in advanced logic devices, it is increasingly important to reduce structural device variation. Structural device variations can be a proxy for device yield. These variations might include critical dimension (CD), gate CD, gate height, and proximity between neighboring vias. One contributor to structural device v... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity
By PDF Solutions - 10 Jun, 2025 - Comments: 0

Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)
By Technical Paper Link - 25 Apr, 2025 - Comments: 0

A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

Controllable Interaction Between Two Hole Spin Qubits In A Conventional Silicon Transistor
By Technical Paper Link - 15 May, 2024 - Comments: 0

A technical paper titled “Anisotropic exchange interaction of two hole-spin qubits” was published by researchers at University of Basel and IBM Research Europe-Zurich. Abstract: "Semiconductor spin qubits offer the potential to employ industrial transistor technology to produce large-scale quantum computers. Silicon hole spin qubits benefit from fast all-electrical qubit control and sweet... » read more

Enabling Advanced Devices With Atomic Layer Processes
By Katherine Derbyshire - 18 Apr, 2024 - Comments: 2

Atomic layer deposition (ALD) used to be considered too slow to be of practical use in semiconductor manufacturing, but it has emerged as a critical tool for both transistor and interconnect fabrication at the most advanced nodes. ALD can be speeded up somewhat, but the real shift is the rising value of precise composition and thickness control at the most advanced nodes, which makes the ext... » read more

ESD Co-Design For 224G And 112G SerDes In FinFET Technologies
By Synopsys - 25 Oct, 2023 - Comments: 0

In addressing the challenges of enhancing ESD resilience for high-speed SerDes interfaces, it's crucial to ensure the implementation of appropriate ESD protection measures. This is particularly vital during the device's lifecycle from the conclusion of silicon wafer processing to system assembly, a phase during which electronic devices are highly susceptible to Electrostatic Discharge (ESD) dam... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs
By Technical Paper Link - 06 Oct, 2023 - Comments: 0

A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Demonstrating The Capabilities Of Virtual Wafer Process Modeling And Virtual Metrology
By Technical Paper Link - 27 Jul, 2023 - Comments: 0

A technical paper titled “Review of virtual wafer process modeling and metrology for advanced technology development” was published by researchers at Coventor Inc., Lam Research. Abstract: "Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the p... » read more

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