Chip Aging Becomes Design Problem


Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

Leti’s Next Focus


Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to discuss R&D trends, a new deal with Soitec, and the latest developments at the France-based research organization. Leti is a research institute of CEA Tech. What follows are excerpts of that conversation. SE: Leti recently formed an alliance with Soitec. Under the terms, Leti and Soitec are formin... » read more

What’s In A Node?


In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading... » read more

The Challenges Of Process Control On FinFETs And FD-SOI


Across the semiconductor industry, both FD-SOI and finFET transistor technologies are in high volume production, with IC manufacturers looking to extend both technologies to gain additional performance improvements and meet the variety of customer specific technical and economic requirements. In developing the processes needed for the next-generation FD-SOI and finFET technologies, both transis... » read more

Supply Monitoring On 28nm & FinFET: The Challenges Posed


A Q&A with Moortec CTO Oliver King. What are the issues with supplies on advanced nodes? The supplies have been coming down, quicker than the threshold voltages which has led to less supply margin. In addition to this, the interconnects are becoming thinner and closer together, which is pushing up resistance and also capacitance. What is the effect of these issues? In short, it... » read more

Thermal Issues And Modern SoCs: How Hot Is Hot?


A Q&A with Moortec CTO Oliver King. What are the thermal issues of modern SoCs? Gate density has been increasing with each node and that pushes up power per unit area, and I think that has become an even bigger issue with FinFET processes where the channels are more thermally isolated than the planar processes before them. In the last few planar nodes, leakage was an issue which led ... » read more

Advanced ASICs: It Takes An Ecosystem


I remember the days of the IDM (integrated device manufacturer). For me, it was RCA, where I worked for 15 years as the company changed from RCA to GE and then ultimately to Harris Semiconductor. It’s a bit of a cliché, but life was simpler then, from a customer point of view at least. RCA did it all. We designed all the IP, did the physical design, owned fabs, assembly and test facilities a... » read more

Exploring New Scaling Approaches


At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography 2017 conference, Semiconductor Engineering sat down to discuss semiconductor technology with Tsu-Jae King Liu, the TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. More specifically, Liu discussed some of the new... » read more

Using Advanced Statistical Analysis To Improve FinFET Transistor Performance


Trial and error wafer fabrication is commonly used to study the effect of process changes in the development of FinFET and other advanced semiconductor technologies. Due to the interaction of upstream unit process parameters (such as deposition conformality, etch anisotropy, selectivity) during actual fabrication, variations based upon process changes can be highly complex. Process simulators t... » read more

Training As A Strategic Weapon


In my last post, I discussed the topic of applying machine learning to the design of machine learning chips. I pointed out that one can achieve significant improvements in schedule predictability, PPA compliance and an overall reduction in program risk if machine learning is applied to the right kind of knowledge base. This is very real, and we are seeing the benefits of this approach daily. Bu... » read more

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