Influence Of SiGe On Parasitic Parameters in PMOS


In this paper, simulation-based design-technology co-optimization (DTCO) is carried out using the Coventor SEMulator3D virtual fabrication platform with its integrated electrical analysis capabilities [1]. In our study, process modeling is used to predict the sensitivity of FinFET device performance to changes in a silicon germanium epitaxial process. The simulated process is a gate-last flow p... » read more

Week in Review – IoT, Security, Auto


Products/Services Synopsys announced successful deployment of the Synopsys Yield Explorer yield learning platform for fast ramp-up of new products on Samsung's advanced finFET technology nodes. Using the secure data exchange mechanism in Yield Explorer, Samsung is able to share the data required for yield analysis, such as chip design, fab, and test, with its customers while maintaining the co... » read more

Controlling Variability And Cost At 3nm And Beyond


Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

Target: 50% Reduction In Memory Power


Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Using Less Power At The Same Node


Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Week In Review: Design, Low Power


Tools & IP OneSpin revealed its latest formal app, Connectivity XL, providing formal connectivity checking to 7nm, multi-billion gate SoC designs. The app generates detailed connectivity specification tables from abstract connectivity specs through a dedicated checking engine that integrates structural and formal analysis to perform on-the-fly, automated abstractions. It supports verificat... » read more

Fundamental Shifts In 2018


What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Designing For Ultra-Low-Power IoT Devices


Optimizing designs for power is becoming the top design challenge in battery-driven IoT devices, boxed in by a combination of requirements such as low cost, minimum performance and functionality, as well as the need for at least some of the circuits to be always on. Power optimization is growing even more complicated as AI inferencing moves from the data center to the edge. Even simple sens... » read more

Finding New Dimensions Of Innovation


Whenever a company announces a major strategy shift and restructuring, such as pivoting away from 7nm FinFET technology development, it’s understandable that confusion, uncertainty and misunderstandings may arise. The best way to allay these concerns is to take an objective look at the situation: Demand for chips for the automotive, IoT, mobility and data center/wireless infrastructure mar... » read more

How To Improve Analog Design Reuse


Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible. Analog design is notoriously difficult and varied. It can include anything from power ma... » read more

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