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Rowhammer: Recent Developments & Future Directions (ETH Zurich)


A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract: "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon i... » read more

Research Bits: Aug. 8


Speeding NVM encryption Researchers from North Carolina State University propose a way to speed up encryption and file system performance for non-volatile memory (NVM). “NVMs are an emerging technology that allows rapid access to the data, and retains data even when a system crashes or loses power,” said Amro Awad, an assistant professor of electrical and computer engineering at North C... » read more

Edge-AI Hardware for Extended Reality


New technical paper titled "Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications" from researchers at Indian Institute of Technology Delhi and Reality Labs Research, Meta. Abstract "Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR w... » read more

What’s In A Name(space)? Optimizing SSD Controller Performance And Verification


Solid state drives (SSDs) have come to the forefront as a promising solution for today and tomorrow’s immense data transfer and storage demands. And SSDs themselves are constantly evolving with upgrades of their critical components to provide higher access speeds. One such component for the NVMe specification is created by the division of non-volatile memory (NVM) into what are commonly known... » read more

Memory Bandwidth Regulation on Hybrid NVM/DRAM Platforms


New technical paper from Shanghai Jiao Tong University Abstract "Non-volatile memory (NVM) has emerged as a new memory media, resulting in a hybrid NVM/DRAM configuration in typical servers. Memory-intensive applications competing for the scant memory bandwidth can yield degraded performance. Identifying the noisy neighbors and regulating the memory bandwidth usage of them can alleviate th... » read more

SOT-MRAM To Challenge SRAM


In an era of new non-volatile memory (NVM) technologies, yet another variation is poised to join the competition — a new version of MRAM called spin-orbit torque, or SOT-MRAM. What makes this one particularly interesting is the possibility that someday it could supplant SRAM arrays in systems-on-chip (SoCs) and other integrated circuits. The key advantages of SOT-MRAM technology are the pr... » read more

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices


Abstract:  "Recent advances in deep learning have been driven by ever-increasing model sizes, with networks growing to millions or even billions of parameters. Such enormous models call for fast and energy-efficient hardware accelerators. We study the potential of Analog AI accelerators based on Non-Volatile Memory, in particular Phase Change Memory (PCM), for software-equivalent accurate i... » read more

All-inorganic perovskite quantum dot light-emitting memories


Abstract "Field-induced ionic motions in all-inorganic CsPbBr3 perovskite quantum dots (QDs) strongly dictate not only their electro-optical characteristics but also the ultimate optoelectronic device performance. Here, we show that the functionality of a single Ag/CsPbBr3/ITO device can be actively switched on a sub-millisecond scale from a resistive random-access memory (RRAM) to a light-e... » read more

More Errors, More Correction in Memories


As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences


Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

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