Why Standard Memory Choices Are So Confusing


System architects increasingly are developing custom memory architectures based upon specific use cases, adding to the complexity of the design process even though the basic memory building blocks have been around for more than half a century. The number of tradeoffs has skyrocketed along with the volume of data. Memory bandwidth is now a gating factor for applications, and traditional memor... » read more

Utilizing Computational Memory


For systems to become faster and consume less power, they must stop wasting the power required to move data around and start adding processing near memory. This approach has been proven, and products are entering the marketplace designed to fill a number of roles. Processing near memory, also known as computational memory, has been hiding in the shadows for more than a decade. Ever since the... » read more

Power/Performance Bits: April 16


Faster CNN training Researchers at North Carolina State University developed a technique that reduces training time for deep learning networks by more than 60% without sacrificing accuracy. Convolutional neural networks (CNN) divide images into blocks, which are then run through a series of computational filters. In training, this needs to be repeated for the thousands to millions of images... » read more

3D NAND Metrology Challenges Growing


3D NAND vendors face several challenges to scale their devices to the next level, but one manufacturing technology stands out as much more difficult at each turn—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems and ensure yields for all chip types. In the case of 3D NAND, the metrology tools are becoming more expensive at each iteration... » read more

January ’19 Startup Funding: $100M+ Rounds Abound


Sixteen companies received private funding rounds of $100 million or more during the month of January, with two privately held companies, Infor and Verily Life Sciences, taking in rounds of $1.5 billion and $1 billion, respectively. The market segments represented in the January rounds were varied. Multiple companies using artificial intelligence technology in their offerings and cloud-based... » read more

Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance


Authors: Fred Ware,(1) Javier Bueno,(2) Liji Gopalakrishnan,(1) Brent Haukness,(1) Chris Haywood,(1) Toni Juan,(2) Eric Linstadt,(1) Sally A. McKee,(3) Steven C. Woo,(1) Kenneth L. Wright,(1) Craig Hampel,(1) Gary Bronner.(1) (1) Rambus Inc. Sunnyvale, California (2) Metempsy, Barcelona, Spain (3) Clemson University, South Carolina Rapidly evolving workloads and exploding data volumes ... » read more

What’s The Outlook for Memory?


What a difference a year makes in the memory business. At this time last year, the industry was in the midst of a boom cycle for both NAND and DRAM. More specifically, there was huge demand for 3D NAND. Then, starting in the first quarter of 2018, the NAND market began to decline and it continues to fall. And now, the DRAM market is also falling off the cliff. So, it’s time to take a q... » read more

Defining Edge Memory Requirements


Defining edge computing memory requirements is a growing problem for chipmakers vying for a piece of this market, because it varies by platform, by application, and even by use case. Edge computing plays a role in artificial intelligence, automotive, IoT, data centers, as well as wearables, and each has significantly different memory requirements. So it's important to have memory requirement... » read more

How To Choose The Right Memory


When it comes to designing memory, there is no such thing as one size fits all. And given the long list of memory types and usage scenarios, system architects must be absolutely clear on the system requirements for their application. A first decision is whether or not to put the memory on the logic die as part of the SoC, or keep it as off-chip memory. "The tradeoff between latency and th... » read more

Mentor TLC NAND Softmodel Soft-Bit Error Injection


Designing SSD controllers targeting NAND flash as the storage media requires some heavy lifting when it comes to dealing with the soft-errors that the flash will eventually produce. This paper will look at a method to simplify the design and verification required. We model these soft-bit behaviors with the Veloce emulator in a virtual setup, which reduces the time to market for an SSD. To r... » read more

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