tag: power optimization

A Power-First Approach
By Brian Bailey - 27 Oct, 2022 - Comments: 6

It is becoming evidently clear that heat will be the limiter for the future of semiconductors. Already, large percentages of a chip are dark at any time, because if everything operated at the same time the amount of heat generated would exceed the ability of the chip and package to dissipate that energy. If we now start to contemplate stacking dies, where the ability to extract heat remains con... » read more

Towards Decarbonization: Keeping Electronics Energy Consumption In Check
By Frank Schirrmeister - 23 Nov, 2021 - Comments: 0

The International Technology Roadmap for Semiconductors (ITRS) roadmap famously said in 2001 that "cost of design is the greatest threat to the continuation of the semiconductor roadmap." For years, the industry followed the ITRS updates on productivity improvements provided by automating design and hardware to counteract the looming design cost. The discussion on decarbonization has some simil... » read more

Data Overload In The Data Center
By Ed Sperling - 25 Jan, 2021 - Comments: 0

Dealing with increasing volumes of data inside of data centers requires an understanding of architectures, the flow of data between memory and processors, bandwidth, cache coherency and new memory types and interfaces. Gary Ruggles, senior product marketing manager at Synopsys, talks about how these systems are being revamped to improve performance and reduce power. » read more

Custom Designs, Custom Problems
By Ed Sperling - 16 Sep, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

For AI Hardware, Power Optimization Starts With Software And Ends At Silicon
By Solaiman Rahim - 04 Sep, 2020 - Comments: 0

Artificial intelligence (AI) processing hardware has emerged as a critical piece of today’s tech innovation. AI hardware architecture is very symmetric with large arrays of up to thousands of processing elements (tiles), leading to billion+ gate designs and huge power consumption. For example, the Tesla auto-pilot software stack consumes 72W of power, while the neural network accelerator cons... » read more

Low-Power Analog
By Brian Bailey - 14 May, 2020 - Comments: 3

Analog circuitry is usually a small part of a large SoC, but it does not scale in the same way as digital circuitry under Moore's Law. The power consumed by analog is becoming an increasing concern, especially for battery-operated devices. At the same time, little automation is available to help analog designers reduce consumption. "Newer consumer devices, like smartphones and wearables, alo... » read more

Utilizing Clock-Gating Efficiency To Reduce Power In RTL Designs
By Mentor, a Siemens Business - 08 Aug, 2018 - Comments: 0

With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are g... » read more

Power Optimization Strategies Widen
By Brian Bailey - 10 May, 2018 - Comments: 0

An increasing amount of electronic content in new and existing markets is creating different and sometimes competing demands for power optimization. For the past decade, EDA has been driven by the mobile phone industry, where the emphasis is on better power analysis and optimization tools to reduce power consumption and extend battery life. While energy efficiency continues to improve, other... » read more

Estimating Power And Performing Optimization
By Guillaume Boillet - 13 Jul, 2017 - Comments: 0

Power analysis and optimization have gained importance over the last few years. During this time it has become obvious how critical it is to use realistic payloads to accurately estimate power and perform optimization tasks. Designers have a range of different objectives and concerns when it comes to power. On one side, a team wants to ensure that the average power of their chip is low enough t... » read more

What Does “Low Power Optimization” Mean To You?
By Dave Pursley - 08 Jun, 2017 - Comments: 0

As I was researching some new low power capabilities, I asked this question of nearly every designer I met: “How important is low power optimization?” It turns out that it’s a pretty useless question because of course it’s important to just about everyone. After all, reducing power improves reliability and reduces design costs. And for chips destined for certain applications, such as mo... » read more

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