ESD Signoff No Longer A “Nice to Have” In FinFET Design Era

Failures in ESD can have a direct impact on first-silicon success.


As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts.

Technology scaling
With technology scaling we are seeing shrinking design windows available for ESD engineers due to narrowing margins between the nominal voltages and device breakdown voltages. Snap-back devices such as GGNMOS and SCR clamps have very low parasitic and are often used in high-speed I/O, RF and critical analog circuits. With finFETs, it is extremely challenging to design snap-back devices — if not impossible. The failure currents in these devices have reduced by 50%, prompting larger ESD devices, which in turn increases the parasitic capacitances and impacts the products’ performance. In addition, thinner interconnects increase the possibilities of wire self-heating, requiring significant layout changes from one process node to another. Looking at the common causes for ESD failures, almost 55% of the failures are interconnect-related and can be avoided by performing systematic ESD checks during design phase.

Changing design trends
Today’s SoCs integrate several IPs such as analog, RF, memories, high-speed I/Os, and processor cores at the SoC level. Each IP that is integrated into the same silicon has different functional requirements, making ESD protection device reuse very challenging. For example, a high speed I/O such as DDR operating at more than 1.5 to 2GHz requires very low parasitic capacitance and different ESD protection compared to traditional I/O. Interface signals between IPs that traverse across power domains need to be protected from ESD discharge events. Similarly, power domains that connect directly to the C4 bumps need core clamps to protect them from discharge. So an ESD protection scheme that worked in one design cannot be re-used for another design or another process.


Higher pin-count, thinner interconnects, gate-oxide, stringent constraints, and multiple power islands make the ESD protection network design challenging in the sub-16nm/finFET era. Correct by construction approaches that worked in the past is no longer a viable solution.

I/O and IP requirements
Companies developing IPs for commonly used peripherals need to ensure that the IP works and meets the specification over different process nodes and foundries for a widespread adoption. Poor ESD protection can negatively impact IP designers’ ability to deliver power, performance and area. A bulky clamp device has higher leakage, occupies more area and has higher parasitics, thus impacting the performance. So, it is not practical to over-design ESD devices or ESD networks. For IP designers, it is significantly challenging to select the right kind of ESD protection scheme that delivers consistent performance over several foundries. Therefore, it is critical to adopt a systematic and simulation-driven ESD verification and validation methodology, especially for finFET designs.

Full-chip SoC requirements
To achieve first-silicon success ESD protection for any integrated circuit, a designer must perform ESD protection evaluation and verification at every stage of the overall design flow. They must ensure robust current handling, low resistance, and that the desired discharge path exists for conduction of ESD current between any two pads.

For designs using finFET devices, the ESD devices will occupy a much larger area compared to functional devices to achieve same level of ESD protection. An early ESD planning and verification allows designers to achieve optimal protection without compromising on area or leakage. In advanced process nodes, a common design trend is to replace a large bulky clamp with small distributed clamps. During the ESD event, all the clamps trigger to discharge the ESD current effectively. Verifying the clamp connections visually or through DRC checks for massively complex 10- or 12-layer metal stacks is not a trivial task. It requires systematic and simulation based checks to ensure the proper connection of ESD devices. Such a solution includes the capacity to handle large designs, accuracy in extraction and ESD device modeling, flexibility to handle different ESD scenarios, and a user-friendly debug environment that helps designers identify and root-cause design weakness.

With increasing wafer costs, first silicon success is critical to any semiconductor company and ESD failures directly impact the first silicon success. ESD sign-off is no longer a “nice-to-have” but a “must-have” requirement. Design for Reliability needs to be an integral part of today’s design methodology to ensure quality ESD signoff from the I/O and IP level all the way to the full-chip SoC.