tag: electrostatic discharge

What To Do About Electrostatic Discharge
By Ed Sperling - 20 Nov, 2023 - Comments: 0

Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

The Ansys Charge Plus PiC Solve
By Ansys - 13 Sep, 2023 - Comments: 0

All surfaces are exposed to radiation, whether aircraft fuselages, satellite skins, or solar panels, are subjected to ionization effects through the accumulation of charged plasmas. Such plasmas present critical hazards to these platforms as their sudden nonlinear discharges can damage or destroy surfaces and underlying electronic components. Through the Particle-in-Cell solver, Ansys Charge Pl... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies
By Synopsys - 07 Jun, 2023 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

Ensuring ESD Protection Verification With Industry-Standard Checks
By Mark Tawfik - 21 Dec, 2022 - Comments: 0

Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance ch... » read more

Are You Paying Proper Attention To Your ESD Design Windows?
By Derong Yan - 10 Nov, 2022 - Comments: 0

Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) chec... » read more

2.5/3D IC Reliability Verification Has Come A Long Way
By Dina Medhat - 01 Aug, 2022 - Comments: 0

2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis
By Neel Natekar - 10 Feb, 2022 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtim... » read more

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?
By Dina Medhat - 23 Sep, 2021 - Comments: 0

Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

The Shortest Path Deception
By Derong Yan - 09 Sep, 2021 - Comments: 1

When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess... » read more

Meeting Automotive Functional Safety Requirements With GPIOs
By Rupal Gandhi - 06 May, 2021 - Comments: 1

Automotive OEMs are building advanced driver assistance systems (ADAS) to improve safety. ADAS systems must meet stringent performance, power, and cost requirements, so the system-on-chips (SoCs) that make up ADAS and passenger safety systems integrate advanced protocols and are built on leading edge finFET process technologies. Designers of this new class of ADAS SoCs are challenged to meet IS... » read more

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