The proper construction and placement of ESD protection circuits is vital to IC performance and reliability.
Electronic design automation (EDA) verification of electrostatic discharge (ESD) protection is a complex task. Different integrated circuit (IC) design companies use different ESD protection approaches, different design flows, and different verification tools. To establish a consistent and comprehensive ESD EDA verification flow, the ESD Association (ESDA) provides recommended ESD compliance checks. Pre-coded packaged checks allow design companies to implement fast, efficient ESD verification without the need to code and maintain their own checks.
Electrostatic discharge (ESD) is the discharge of static electrical current when two objects come into contact. A commonplace example of ESD is the shock we get when we walk over a carpet and touch a metal doorknob. A more powerful illustration of an ESD event is a lightning strike. Unless you routinely stand outside in a thunderstorm holding a metal pole aloft, chances are that most ESD events you encounter will only result in negligible effects. Unfortunately, the same is not true in the semiconductor industry.
ESD events are a costly issue in numerous situations in the semiconductor industry. Most electronic devices are vulnerable to damage caused by even low voltage ESD events. For this reason, producers of electronic components incorporate measures to avoid ESD events all throughout the manufacturing process, testing, shipping, and product use. For example, workers may wear an ESD safety wrist strap or footwear when working with these devices, or stand on an ESD carpet, to ensure that any electrostatic charge goes into the ground rather than into the device. Sensitive devices are stored and shipped with materials that protect the item from absorbing a charge.
To provide similar protection at the integrated circuit (IC) level, design companies include ESD protection circuits in the device designs. ESD events can damage IC circuitry, which can reduce device performance or result in total failure, so protecting ICs against ESD effects is an essential component of the IC design process. However, to ensure that these protection circuits work as intended, designers must verify their construction against design rules that define the proper construction and placement of these circuits.
In the past, many companies wrote and maintained their own ESD rules and checks, a time-consuming and resource-intensive operation requiring significant expertise in both ESD protection design and rule writing. That approach is changing with the help and guidance of industry organizations like the ESD Association (ESDA).
The ESDA is a voluntary professional association dedicated to advancing the understanding of the theory and practice of ESD avoidance. To provide guidelines for both the electronic design automation (EDA) industry and ESD design community, and to establish a comprehensive ESD EDA verification flow that satisfies modern ESD design challenges, the ESDA provides a standardized list of important design rules and corresponding compliance checks to help IC design teams protect their layouts from damage caused by ESD events [1].
According to the ESDA, an ideal EDA ESD verification flow should include:
All levels of potential ESD in an IC design must be evaluated and verified, from device-level to full-chip level. The ESDA rules are divided into four main checks categories, each focusing on specific reliability targets:
By providing these rules and their associated checks, the ESDA helps design companies implement standardized, thorough ESD verification across all designs and technology nodes, while minimizing the need for custom check coding and maintenance.
Protected circuit checks define generic topologies that are prone to fail during an ESD event, and verify that they are properly protected [1]. Examples of these topologies include pad-connected gate oxides, decoupling capacitors, gates along power cross-domains paths, and weak devices. Weak devices include devices containing metal oxide semiconductor (MOS) technology (e.g., DeNMOS, LDMOS, etc.), which means they have very high impedances that do not allow the charge to dissipate in a more controlled fashion, or devices with a small width, which makes them very sensitive to ESD impacts. Figure 1 lists the ESDA protected circuit checks.
Fig. 1: ESDA protected circuit checks. Checks are named based on the rule numbers assigned by the ESDA.
Cell-level ESD checks focus on verifying the intended ESD protection path within a standalone cell. They are mainly defined by process, ESD design, and latch-up design rules. A robust set of basic technology process rules clearly defining process and device material limits is a necessary foundation of ESD verification at the cell level. Best practice recommendations suggest running these checks on the schematic design data of ESD cells to catch any design flaws at early stages. However, certain checks (e.g., resistance extraction) must be performed on the cell layout [1]. Figure 2 lists the ESDA cell-level checks.
Fig. 2: Cell-level checks. Checks are named based on the rule numbers assigned by the ESDA.
Intra-power-domain checks verify the compliance of an I/O domain (cells within the same power supply domain) with ESD-specific rules. These checks start with verification of the latest intellectual property (IP) library version, move to the placement of bumps/protections, then resistance checks of the I/O bank, and finally, a first-order calculation of the voltage drop for each pin-pair combination [1]. Figure 3 lists the ESDA intra-power-domain checks.
Fig. 3: Intra-power-domain checks. Checks are named based on the rule numbers assigned by the ESDA.
Inter-power-domain ESD checks ensure that every pin combination on the chip has a designated ESD current path, including pairs of pins belonging to different power domains. Potential problems with ESD voltage drops are already partially addressed by ensuring compliance with the intra-power-domain checks for each individual power domain. However, designers must ensure that the correct transition cells are placed between power domains [1]. Figure 4 lists the ESDA inter-power-domain checks.
Fig. 4: Inter-power-domain checks. Checks are named based on the rule numbers assigned by the ESDA.
However, simply having the ESDA checks available is only the first step. Understanding how to set up and run these checks in their environment can still be challenging for designers. To further simplify and standardize the use of the ESDA checks, electronic design automation (EDA) companies like Siemens EDA encapsulate the ESDA checks into pre-coded packaged checks that can be easily added to a design team’s reliability verification flow [2].
To provide consistent and accurate coverage of the ESDA rules, the Calibre PERC platform [3] provides pre-coded packaged checks for each of the four ESD coverage categories. Designers can invoke these checks using either the default parameters or a range of desired modifications, eliminating the need for manually-coded checks while ensuring coverage for any proprietary design requirements.
Using the Calibre PERC reliability platform, designers can embed reliability checks into their existing design flows as part of an integrated Calibre flow for cell, square, and full-chip verification [4]. Bringing together rules coded in both the standard verification rule format (SVRF) and the Tcl-based Tcl verification format (TVF) language across all applications provides designers with the flexibility and adaptability required to meet the particular and advancing needs of their design teams, while guaranteeing compatibility with all foundries [5,6].
Design teams can run any combination of Calibre PERC packaged ESD checks, then analyze and debug the results using the Calibre RVE results viewer.
Fig. 5: Results for multiple Calibre ESD checks are displayed in the Calibre RVE results viewer.
ESD is a very real and present danger to the performance and reliability of ICs. The ESDA provides guidelines for both the EDA industry and ESD design community to establish a comprehensive EDA verification flow that satisfies the ESD design verification challenges of modern ICs [1]. Pre-coded checks like the Calibre PERC packaged ESDA checks from Siemens EDA provide a way to apply the ESDA guidelines quickly and accurately, enabling designers to run comprehensive ESD verifications on any technology node for any design level. By using EDA options like the Calibre PERC packaged ESDA checks, designers can achieve fast, accurate ESD reliability verification while reducing time to market.
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