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Enhance IC Reliability Design Verification With Coordinate-Based P2P And CD Checking


Coordinate-based P2P and CD checks with the Calibre PERC reliability platform enable quick early-stage design verification of ESD protection and other IC reliability issues. Using coordinate-based checking minimizes the amount of rule deck coding required, enabling design teams to start Calibre PERC P2P/CD verification very quickly, and understand and debug the results easily. Because P2P/CD ch... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification


Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?


Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

How Robust Is Your ESD Protection? Are You Sure?


Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more

Power Grid Analysis Heats Up At 20nm


By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

Dangerous Electricity


Electricity to the modern age is as indispensible as air, but too much can be a bad thing for automotive and aerospace applications—especially when it is in the form of electrostatic discharge (ESD). As chips advance to 28nm, 20nm and 16nm, the design window for electrostatic discharge is shrinking for a number of reasons, explained Norman Chang is vice president and senior product strategis... » read more