How Robust Is Your ESD Protection? Are You Sure?

Electrostatic discharge protection is more important than ever. New verification methods can help.


Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increasing challenges when checking ESD protection requirements and interconnect strength, not only at the intellectual property (IP) and large block levels, but all the way to full-chip verification. New tools and techniques are easing the burden of ESD verification and improving product reliability.

Everyone who’s ever walked across a carpet then gotten a shock when they touched a doorknob knows exactly what an ESD event is. In an integrated circuit (IC), an ESD event typically induces electrical currents on the order of 0.1–10 amps, which lasts between 10-6 and 10-3 seconds, and dissipates energy on the order of 10–100 watts. ESD protection methods shunt these ESD currents through unpowered devices (ESD protection devices) along intended ESD discharge paths, while clamping the voltage at a safe level, preventing any functional degradation to the protected devices.

Typical ESD protection schemes are shown in Figure 1. The common ESD discharge paths (highlighted in green) run between:

  1. I/O bump and power clamp
  2. I/O bump and power bump
  3. power bump and ground bump
  4. ESD resistor and power clamp
  5. I/O bump and I/O bump

In layouts (a)-(d), the I/O pad is protected by pull-up and pull-down diodes, an ESD resistor, and secondary ESD diodes. A power clamp is connected between power bus VDD and ground bus VSS. In layout (e), a pair of back-to-back (B2B) connected diodes are used to connect the ground busses VSSA and VSSB from two power domains.

Figure 1. Common ESD protection schemes.

In the event of an over-voltage incident on the I/O pad in Figure 1:

  1. The overflow of electric charge shunts through the pull-up diode, and dissipates through the power clamp. For the pull-up diode to effectively shunt the ESD currents, the total resistance value of R0+R1+R3+R7+R9 must be within a maximum allowed limit.
  2. The overflow of electric charge shunts through the pull-up diode, and dissipates through the VDD power source. The total resistance value of R0+R1+R3+R7+R11 must be within a maximum allowed limit.
  3. The possible ESD discharge path runs between power pad VDD and ground pad VSS, which goes through the power clamp. The total resistance value of R11+R9+R10+R12 must be within a maximum allowed limit.
  4. The possible ESD discharge path starts from the ESD resistor, passes through secondary ESD protection (i.e., a pull-up diode), and ends at the power clamp. The total resistance value of R5+R7+R9 must be within a maximum allowed limit.

In (a)-(d), all metal interconnects and vias along the ESD discharge path must be robust enough to withstand the ESD currents during the ESD event.

  1. The possible ESD discharge path starts at I/O pad A, goes through a pull-up diode, a power clamp, the B2B diode, the ground bus VSSB, a pull-down diode, and eventually ends at I/O pad B. Not only must all metal interconnects and vias along this ESD discharge path be robust enough to withstand the ESD currents, but their effective total resistance value must be within a maximum allowed limit.

From an SoC design perspective, all ESD discharge paths can be categorized into one of four categories (Figure 2):

  • at cell level (e.g., within a standard cell)
  • within same power domain (e.g., within a block)
  • across different power domains (e.g., across multiple blocks or at full chip level)
  • at package level

Figure 2. Typical ESD discharge paths in SoC designs. (Source: EOS/ESD Association. Used by permission.)

ESD protection verification
Typical verification of ESD protection includes:

  1. Verifying ESD protection devices, including their existence on ESD paths, versions and structures, placements, etc.
  2. Verifying the devices that require ESD protection, including their connections to ESD protection devices, versions and structures, placements, etc.
  3. Verifying robustness of metal interconnects and vias along ESD discharge paths.
  4. Verifying the resistances of ESD discharge paths are within allowed design limits.

Historically, design companies wrote their own ESD verification rule decks, and used design rule checking (DRC), layout vs. schematic (LVS), and electrical rule checking (ERC) tools to perform the ESD checks. However, this approach had three significant flaws:

  • Each company interprets and implements ESD protection requirements differently, which makes it difficult for the foundries to ensure that adequate ESD protection is in place.
  • Writing and maintaining a custom rule deck consumes valuable time and resources.
  • Each of the verification tools used is designed to check one specific aspect of a design (physical configuration, circuit performance, etc.), but verifying ESD protection requires a holistic view of both physical and electrical design characteristics.

The first step to a comprehensive ESD verification solution was to develop the means to obtain unified access to all the relevant types of design data (i.e., physical, logical, electrical) in a single environment. This combination enables the evaluation of topological constraints within the context of physical requirements. New electronic design automation (EDA) verification tools like the Calibre PERC reliability platform can now combine physical and electrical information in a single analysis to support advanced ESD protection verification.

Next, the foundries had to begin providing standardized rule decks for these tools. In addition to providing a repeatable, comprehensive, and efficient ESD verification process from the first schematic through SoC assembly to the final layout, these decks also freed the design companies from the burden of developing and maintaining custom decks. Such rule decks typically check for the existence and connectivity of ESD devices, latch-up requirements, maximum current densities and maximum point-to-point resistance values along ESD discharge paths, and more.

Maximum current density (CD) and maximum point-to-point (P2P) resistance value along ESD discharge paths are critical constraints in ESD protection schemes. Calculating these values requires topology information from the layout design, such as ESD devices (e.g., pull-up and pull-down diodes, power clamps, etc.), and the locations of I/O, power, and ground pads, etc. A typical automated ESD verification flow (Figure 3) includes steps such as the following:

  • Extract layout netlist from the layout design database.
  • Run topology analysis to identify I/O, power and ground pads, and ESD devices (such as pull-up and pull-down diodes, power clamps, etc.). All ESD discharge paths are identified based on their definitions in the rule deck.
  • Run circuit simulation to calculate the effective resistances of ESD discharge paths (P2P flow), and the current densities on each segment along the ESD discharge paths (CD flow).
    • For P2P, calculate the effective total resistance value of each ESD discharge path of interest, and compare that value to the maximum allowed limit. If the effective total resistance value is greater than the limit, flag a violation.
    • For CD, the values of ESD currents that may occur during ESD events of interest are specified in the rule deck, based on the ESD models used. Each value represents the maximum amount of electrical current that will dissipate through a particular ESD discharge path during a particular ESD event. Based on this ESD current value, calculate the ESD current density on each segment along the ESD discharge path. If the ESD current density is greater than the maximum allowed limit on the segment (determined by process technology), flag a violation.

Figure 3. P2P and CD verification flow.

ESD protection is more critical than ever for today’s electronic products, which must perform reliably under a wide variety of demanding environments and conditions. Traditional ESD verification methods lack the ability to combine physical and electrical information for accurate analysis of potential ESD conditions in designs, and rely on custom rule decks that require significant time and resources from design companies. New ESD verification methods and tools can automatically identify and accurately analyze ESD protection topologies in the input schematic or layout design, while foundry-provided ESD verification rule decks ensure consistency and accuracy across the industry. If your product reliability is essential to your bottom line, you need a comprehensive and dependable ESD verification strategy.

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