Derong Yan

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Derong Yan is a principal product engineer in the Calibre Design Solutions Division of Siemens EDA, a part of Siemens Digital Industries Solutions. His primary focus is the Calibre PERC reliability platform and reliability verification strategy. Areas of expertise include SoC physical design and verification, reliability verification, and design automation. Before joining Siemens, Yan worked for multiple semiconductor companies. He holds a Ph.D. in Materials Engineering from the University of Alberta and received both his M.Sc. and B.Sc. from Shanghai Jiao Tong University.

Author's Latest Posts

Are You Paying Proper Attention To Your ESD Design Windows?

By Derong Yan - 10 Nov, 2022 - Comments: 0

Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) chec... » read more

The Shortest Path Deception

By Derong Yan - 09 Sep, 2021 - Comments: 1

When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess... » read more

How Robust Is Your ESD Protection? Are You Sure?

By Derong Yan - 08 Feb, 2018 - Comments: 0

Electrostatic discharge (ESD) protection is critical at advanced nodes to safeguard designs against effects intensified by shrinking transistor dimensions and oxide layer thicknesses. On the other hand, ESD protection checks are consuming vastly more runtime and memory due to the growing die sizes of system-on-chips (SoCs) and the number of transistors they can hold. Designers are facing increa... » read more