How Qualcomm Got Faster Signoff DRC Convergence

A case study on improving DRC during base layers tapeout and managing IP interface DRC errors.


Qualcomm Incorporated designs and markets wireless telecommunications products and services that are the foundational technologies that others build upon, from mobile processors to embedded platforms, Bluetooth products, and cellular modems. In the fast-moving mobile phone market in which Qualcomm competes, companies who can get to market more quickly gain a strong competitive advantage, along with the additional profit that comes from being first. Faced with relentless advances in technology, the need for constant product innovation, and rapidly shifting market demand, Qualcomm continually strives to optimize their integrated circuit (IC) design flows to achieve maximum efficiency using the most effective level of resources.

Achieving signoff design rule checking (DRC) convergence in digital implementation flows at advanced nodes is extremely challenging, due to the number and complexity of the DRC rules, and the increasing functionality implemented in designs. Traditionally, DRC flows are set up for full-chip runs, and are not optimized for immediate DRC feedback on select design windows. Qualcomm saw an opportunity to optimize their digital implementation DRC process and achieve faster signoff DRC convergence by adding Calibre RealTime Digital in-design signoff DRC to their design and verification flow.

Qualcomm’s challenges and opportunities
Qualcomm’s system-on-chip (SoC) designs are constantly getting larger and becoming more complex. The increasing size and complexity of designs made it challenging to perform signoff-quality DRC in place and route (P&R) while also achieving the turnaround time needed to reach signoff DRC convergence on schedule.

Their existing P&R signoff DRC closure flow consisted of three primary stages:

  • Export P&R data
  • Merge P&R data with intellectual property (IP) data and generate a merged GDSII/OASIS database
  • Run signoff DRC against the GDSII/OASIS database

While this flow is optimized for DRC runs on full-chip and large blocks, exporting the P&R data and merging it with the IP data is time-consuming, which can extend the physical verification feedback cycle and delay convergence during critical SoC milestones.

The Calibre RealTime Digital interface provides direct calls to Calibre analysis engines running foundry-qualified signoff rule decks. These engines perform fast, incremental checking in the vicinity of shapes being edited, providing nearly instantaneous feedback on DRC violations. This immediate feedback in the P&R domain can help Qualcomm achieve shorter DRC closure cycle times while still ensuring signoff DRC confidence.

Qualcomm saw opportunities for significant improvements in two primary use cases:

  • DRC during base layers tapeout
  • IP interface DRC during metal layers tapeout

DRC during base layers tapeout

Block placement
During digital design implementation, most design teams use DRC functionality built into a P&R tool to fix DRC violations in the layout. However, these P&R checkers do not typically perform DRC on the base layers, for the simple reason that these layers are not present in the P&R environment. During floorplanning and placement stages, however, P&R engineers want to place their blocks so they don’t create any new base layer DRC violations, which can be hard to fix later in the design flows. Using the Calibre RealTime Digital interface, Qualcomm engineers can perform a quick DRC pass to catch any base layer DRC errors, and then change their block placements to avoid these errors. Their goal is not to fix the base layer DRC errors, but rather to simply avoid creating them by optimum placements of their blocks.

Base layer debugging
When fixing DRC errors during base layer tapeout, it is a common practice to add tap-cells, move standard cells, and add, delete, or resize filler cells. To fix base layer DRC errors, P&R engineers must currently exit the P&R environment and make the DRC fixes in a separate tool, such as a layout viewer. This process is both tedious and time-consuming, and extends the DRC closure turnaround time for the base layer tapeout. The interface provides immediate base layer Calibre signoff DRC feedback within the P&R environment (Figure 1). With this feedback, P&R engineers can perform a what-if analysis on a DRC violation and make an optimum signoff DRC fix instantly.

Figure 1. Base layer Nwell DRC marker and its applicable Nwell shapes in memory IP, shown in the P&R environment after a DRC run.

Adding IP blocks
New IP blocks are often added after critical design milestones, which can result in Nwell, diffusion, and fin boundary-related DRC violations. Using the IP merge capability, Qualcomm P&R engineers can read the GDS/OASIS data of the IP blocks and provide DRC feedback on the base layers. This enables P&R engineers to check and fix base layers DRC violations upstream in the digital design flow, during floorplanning and placement stages. At these design stages, P&R engineers can use the Calibre RealTime Digital interface to create a floorplan and block placements devoid of DRC violations that would be difficult to fix later in the design flow. This saves P&R engineers valuable time, and eliminates the stress of trying to fix DRC violations caused by structural problems. With the signoff DRC feedback, Qualcomm P&R engineers can easily handle DRC closure for base tapeouts within one to two iterations over several hours, as compared to days with their traditional DRC closure flow.

Interface DRC during metal layers tapeout
A common challenge during traditional DRC debug is managing interface DRC errors that occur between P&R and IP shapes. False DRC errors are typically caused by mismatches between abstract (LEF) and GDSII/OASIS databases, but identifying and removing these false DRC errors from the real DRC errors is another tedious and time-consuming process. P&R engineers cannot see the IP shapes contributing to the DRC violation in the P&R environment. They must open the GDSII/OASIS view of the IP in a separate layout viewer, then navigate to the DRC violation in both the layout viewer and the P&R environment to visually compare the layouts and make a DRC fix. After the DRC fix, they must generate the merged P&R and IP data, launch a signoff DRC run, and wait for hours to learn the impact of their manual DRC fixes.

The process becomes further complicated the closer they get to metal layers tapeout, when interface DRC errors can be buried within the huge number of metal DRC errors caused by interaction among the metal routes within the P&R environment. If these interface DRC errors are not found until late in the design cycle, they can force P&R engineers to make costly changes to the IP blocks, which can delay tapeout by days.

The IP merge flow allows Qualcomm P&R engineers to run signoff base and metal layer DRC checks on the GDSII/OASIS views of the IP blocks within the P&R environment (Figure 2).  The IP shapes relevant to the DRC violation are shown in the P&R interface, which is especially useful for understanding complex DRC rules more quickly. As a result, fixing becomes very intuitive, allowing the engineers to make optimum signoff DRC fixes and instantly validate the fixes in the P&R environment, as opposed to waiting through hours of standalone runs.

Figure 2: In-design verification helps Qualcomm P&R engineers visually debug complex IP interface DRC errors.

In-design physical verification also provides fast validation of via spacings. A P&R native DRC run returned no DRC violations on the via array, but running a Calibre RealTime Digital job in the IP merge flow revealed that there are real signoff DRC violations on the via array (Figure 3).

Figure 3: Real via spacing signoff DRC errors were caught using in-design verification.

The interactive and immediate signoff DRC feedback provided by the Calibre RealTime Digital interface helped Qualcomm achieve faster signoff convergence inside the P&R environment. By eliminating the gaps between the P&R tool’s built-in design rules, and the foundry-qualified rule deck, Qualcomm engineers can now achieve critical milestones, such as base layers and metal layers tapeouts, within their planned schedules.

The solution enables Qualcomm to validate manual physical verification fixes with extremely quick turnaround time, leading to shorter DRC closure cycles. The IP merge flow expands the DRC coverage in P&R by enabling base layers signoff DRC validation. In addition, engineers can confidently make and validate optimum manual metal interface DRC fixes within the P&R environment, eliminating the tedious process of removing false DRC errors caused by incomplete abstracts from the list of real DRC errors. By adding in-design verification solution to their flow, Qualcomm was able to get immediate signoff DRC feedback on targeted window-based DRC fixes before generating the merged P&R and IP data and launching a complete signoff DRC run on the merge data.

Because they can now iterate through signoff DRC in the implementation environment, Qualcomm designers are eliminating a minimum of three to five DRC closure iterations during every critical design milestone, which can save weeks off the tapeout cycle for large SOC designs. And, because the Calibre RealTime Digital interface uses the same Calibre nmDRC signoff deck and engine used in established physical verification flows, Qualcomm can be confident that their designs will meet all manufacturing requirements. No matter which use model they apply, the interface enables Qualcomm engineers to spend less time fixing DRC errors, providing more time to create innovative, high-quality designs that reach the market on schedule.

For full details on how Qualcomm achieved faster signoff convergence, download our whitepaper Qualcomm achieves faster signoff DRC convergence in P&R with Calibre RealTime Digital DRC.

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