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A New Breed Of EDA Required


While doing research for one of my stories this month, a couple of people basically said that applying methodologies of the past to the designs of today can be problematic because there are fundamental differences in the architectures and workloads. While I completely agree, I don't think these statements go far enough. Designs of today generally have one of everything — one CPU, one accel... » read more

Traceability Is Not My Problem (Is It?)


What is all the fuss about traceability? If it is that important, should it be handled by a compliance group? Delegating to a separate team would be the preference for most design and verification team members, but it is not possible in this case. Traceability stops short of a big brother organization constantly looking over the shoulders of the development team. The more reasonable approach is... » read more

IP Industry Transformation


The design IP industry is developing an assortment of new options and licensing schemes that could affect everything from how semiconductor companies collaborate to how ICs are designed, packaged, and brought to market. The IP market already has witnessed a sweeping shift from a "design once, use everywhere" approach, to an "architect once, customize everywhere" model, in which IP is highly ... » read more

Who Benefits From Chiplets, And When


Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

Bridging IC Design, Manufacturing, And In-Field Reliability


Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management and how that can potentially glue together design, manufacturing, and devices in the field, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer sci... » read more

Cybersecurity: The Case For Hardware-Based Threat Detection And Mitigation


The requirements of cyberphysical systems place great responsibility on design teams. Their mission-critical roles in controlling mechanical systems, from aircraft though motor vehicles to industrial plants, have always called for safety-focused design. As these systems have become connected to the internet, safety has become intertwined with security. One mechanism for detecting suspicious ... » read more

Automation Of Shared Bus Memory Test With Tessent MemoryBIST


New requirements in automotive, artificial intelligence (AI), and processor applications have resulted in increased use of memory-heavy IP. Memory-heavy IPs for these applications are optimized for high performance, and they will often have a single access point for testing the memories. Tessent MemoryBIST provides an out-of-the-box solution for using this single access point, or shared bus int... » read more

Expedera: Custom Deep Learning Accelerators Through Soft-IP


Internet of Things (IoT) and Artificial Intelligence (AI) have caused a massive increase in data generation — and along with it, a need to process data faster and more efficiently. Dubbed a “tsunami of data,” data centers are expected to consume about one-fifth of worldwide energy before 2030. This data explosion is driving a wave of startups looking to gain a foothold in custom accele... » read more

Cataloging IP In The Enterprise


Many companies have no way of documenting where IP they license is actually used, which version of that IP is being utilized, and whether that license extends to other projects or even to their customers. Pedro Pires, applications engineer at ClioSoft, looks at how IP currently is cataloged, why it’s been so difficult to do this in the past, and how AI can be used to speed up and simplify thi... » read more

Machine Learning Showing Up As Silicon IP


New machine-learning (ML) architectures continue to appear. Up to now, each new offering has been implemented in a chip for sale, to be placed alongside host processors, memory, and other chips on an accelerator board. But over time, more of this technology could be sold as IP that can be integrated into a system-on-chip (SoC). That trend is evident at recent conferences, where an increasing... » read more

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