tag: IP

Delivering Automotive-Grade Quality With Customized FinFET Foundation IP
By Andrew Appleby - 04 Jun, 2026 - Comments: 0

By Andrew Appleby, Daryl Seitzer, and Nafiz Ahmed The growing compute demands of modern vehicles are forcing chipmakers to venture into new territory. To deliver increased processor performance for engine and body control systems, one leading semiconductor supplier knew it had to move to an automotive-qualified FinFET technology process — a leap that would introduce significant new desi... » read more

Hardware From Specifications Using AI
By Brian Bailey - 06 May, 2026 - Comments: 0

There is a lot of excitement these days surrounding the idea that AI could make it possible to go from a specification to a design with absolutely no hardware skills. Well, get in line, because this is the umpteenth potential technology that was going to make that possible. Don't get me wrong, it just might do it, but will this be an implementation that is reliable, have decent performance, ... » read more

EDA And IP Numbers Up Again, But Numbers Are More Nuanced
By Ed Sperling - 13 Apr, 2026 - Comments: 0

EDA and Semiconductor IP revenue grew 10.3% in Q4 2025 to $5.466 billion, up from $4.955 billion in the same period in 2024, continuing the double-digit run for the tools and IP business that has been underway for the past few years. CAE, the largest EDA category, rose 9.4% to $2.083 billion in Q4, versus $1.761 billion in Q4 2024. Non-reporting IP companies — a segment dominated by Arm �... » read more

IP Requirements Evolve For 3D Multi-Die Designs
By Madhumita Sanyal - 26 Mar, 2026 - Comments: 0

As Moore’s Law continues to slow and demand for compute density and bandwidth accelerates, the semiconductor industry is rapidly shifting from monolithic SoCs to 3D multi-die designs. While 2.5D integration has extended system scaling, it is no longer sufficient to meet the bandwidth, latency, and power requirements of AI, HPC, and advanced automotive applications. The move to true 3D multi-d... » read more

Customizing Foundation IP For Ultra-Low-Voltage Designs
By Daryl Seitzer - 12 Mar, 2026 - Comments: 0

By Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer Building a new system-on-chip (SoC) starts with assembling the right foundational elements—pre‑verified IP for logic, memory, I/O, and other essential functions. Standard IP solutions typically address most common design needs, but some projects call for more specialized approaches, especially when innovation is critical or when t... » read more

Accelerate Your IP Selection With Smart Solido Library Profiler
By Siemens EDA - 02 Mar, 2026 - Comments: 0

This white paper discusses the IP selection process, its requirements, challenges, and proposed solutions. The process of choosing cell IP libraries for integrated circuit (IC) design is a slow and complicated process due to the inconsistencies and complexities of library files, particularly across sources, technology nodes, and variants. Manual methods to achieve IP selection not only consumes... » read more

How IP Subsystems For Chiplets Will Unlock Your Next Wave Of Innovation
By Robert Kruger - 26 Feb, 2026 - Comments: 0

After many years of hope, promises, and commercial challenges, a robust environment that supports multi-die design is now taking shape. These events represent a sea of change for semiconductor design and manufacturing when compared to the traditional single-die monolithic design approach. Moore’s Law drove these original and substantial monolithic design accomplishments. But the massive requi... » read more

Power Leadership At 2nm: Foundation IP Optimized For Next-Gen Hyperscale SoCs
By Andrew Appleby - 12 Feb, 2026 - Comments: 0

By Andrew Appleby and Daryl Seitzer As demand for data center compute accelerates, power efficiency has become the defining metric for modern CPUs, GPUs, and AI accelerators. Every watt saved directly impacts the massive operating costs of gigawatt-scale AI data centers, where power and cooling account for 40–60% of operational expenditures. To reduce energy consumption and strengthen t... » read more

Heterogeneous Multicore System IP
By Nayan Gaywala - 29 Jan, 2026 - Comments: 0

For many of today’s embedded applications, compute requirements demand multiple cores (compute units). These applications also run various types of workloads. A heterogeneous multicore system enables designers to reduce energy and area costs while meeting performance requirements across various workloads. Data crunching by these multiple cores also puts a huge demand on the interconnect and m... » read more

Exploring The Latest Innovations In MIPI D-PHY And MIPI C-PHY
By Michael Nagib - 15 Jan, 2026 - Comments: 0

By Michael Nagib and Nuno Martins In the ever-evolving landscape of high-performance camera and display technologies, MIPI D-PHY and MIPI C-PHY specifications continue to lead the charge, setting benchmarks for low power, low latency, and high bandwidth data transmission. Building on the insights from our previous article, “Demystifying MIPI C-PHY/D–PHY Subsystem” – we now delve into... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy