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Compute Express Link (CXL)

Interconnect between CPU and accelerators.
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Description

Compute Express Link (CXL) is an interconnect specification for CPU-to-Device and CPU-to-Memory designed to improve data center performance.

Built upon PCIe, CXL provides an interconnect between the CPU and platform enhancements and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions. CXL maintains memory coherency between the CPU memory space and memory on attached devices, which according to the Consortium allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost.

CXL supports dynamic multiplexing between a set of protocols that includes I/O (CXL.io, based on PCIe), caching (CXL.cache) and memory (CXL.memory) semantics. CXL maintains a unified, coherent memory space between the CPU (host processor) and any memory on the attached CXL device. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. The CPU is primarily responsible for coherency management.

CXL is managed by the Compute Express Link Consortium and was first introduced in March 2019. The latest version of the specification is available to CXL Consortium member companies, with an evaluation version available.

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The New CXL Standard