How formal verification was used to verify the implementation of design IP for emerging PCIe 5.0 and CXL 2.0 standards.
We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building blocks. The Compute Express Link (CXL) 2.0 specification by the CXL Consortium is one such standard defining high-speed, low-latency, cache-coherent interconnects based on the PCI Express (PCIe) 5.0 protocol. In this white paper, we will examine how formal verification techniques have been successfully deployed to verify the implementation of Cadence design IP for these emerging standards.
By Hamish Hendry, Sakthivel Ramaiah, Derek McAulay, Gary Dick, Cadence
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