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CXL 3.0: From Expansion To Scaling


At the Flash Memory Summit in August, the CXL Consortium released the latest, and highly anticipated, version 3.0 of the Compute Express Link (CXL) specification. This new version of the specification builds on previous generations and introduces several compelling new features that promise to increase data center performance and scalability, while reducing the total cost of ownership (TCO). ... » read more

Compute Express Link (CXL): All You Need To Know


An in-depth look at Compute Express Link  (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. We discuss how CXL technology maintains memory c... » read more

Choosing The Right Server Interface Architectures For High Performance Computing


The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

Sweeping Changes Ahead For Systems Design


Data centers are undergoing a fundamental change, shifting from standard processing models to more data-centric approaches based upon customized hardware, less movement of data, and more pooling of resources. Driven by a flood of web searches, Bitcoin mining, video streaming, data centers are in a race to provide the most efficient and fastest processing possible. But because there are so ma... » read more

CXL Signals A New Era Of Data Center Architecture


An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Improving Power & Performance Beyond Scaling


Steven Woo, Rambus fellow and distinguished inventor, discusses architectural changes inside of servers and data centers to allow pooling of resources such as memory. That has a big impact on power efficiency and overall performance, but it also allows data centers to customize their architectures and prioritized resources with much more granularity than they can do today. » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification


We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

CXL: Sorting Out The Interconnect Soup


In the webinar Hidden Signals: Memory and Interconnect Decisions for AI, IoT and 5G, Shane Rau of IDC and Rambus Fellow Steven Woo discussed how interconnects were a critical enabling technology for future computing platforms. One of the major complications was the “interconnect soup” of numerous and divergent interface protocols. The Compute Express Link (CXL) standard offers to sort out m... » read more

Week In Review: Design, Low Power


The CXL Consortium published the Compute Express Link 2.0 specification. CXL is an interconnect that maintains memory coherency between the CPU memory space and memory on attached devices. CXL 2.0 adds support for switching for fan-out to connect to more devices, memory pooling for increased memory utilization efficiency and providing memory capacity on demand, and support for persistent memory... » read more

Week In Review: Design, Low Power


M&A Synopsys acquired Moortec, a provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. Moortec's sensors will be a key component to Synopsys' new Silicon Lifecycle Management (SLM) platform. "This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for de... » read more

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