tag: Compute Express Link

Improving Power & Performance Beyond Scaling
By Ed Sperling - 16 Jun, 2021 - Comments: 0

Steven Woo, Rambus fellow and distinguished inventor, discusses architectural changes inside of servers and data centers to allow pooling of resources such as memory. That has a big impact on power efficiency and overall performance, but it also allows data centers to customize their architectures and prioritized resources with much more granularity than they can do today. » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification
By Cadence - 09 Jun, 2021 - Comments: 0

We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

CXL: Sorting Out The Interconnect Soup
By Tim Messegee - 11 Feb, 2021 - Comments: 0

In the webinar Hidden Signals: Memory and Interconnect Decisions for AI, IoT and 5G, Shane Rau of IDC and Rambus Fellow Steven Woo discussed how interconnects were a critical enabling technology for future computing platforms. One of the major complications was the “interconnect soup” of numerous and divergent interface protocols. The Compute Express Link (CXL) standard offers to sort out m... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Jan, 2021 - Comments: 0

The CXL Consortium published the Compute Express Link 2.0 specification. CXL is an interconnect that maintains memory coherency between the CPU memory space and memory on attached devices. CXL 2.0 adds support for switching for fan-out to connect to more devices, memory pooling for increased memory utilization efficiency and providing memory capacity on demand, and support for persistent memory... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Nov, 2020 - Comments: 0

M&A Synopsys acquired Moortec, a provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. Moortec's sensors will be a key component to Synopsys' new Silicon Lifecycle Management (SLM) platform. "This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for de... » read more

The New CXL Standard
By Ed Sperling - 16 Sep, 2019 - Comments: 0

Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Mar, 2019 - Comments: 0

M&A Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker's history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Me... » read more

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