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Formal Verification Ensures The Perseverance Rover Lands Safely On Mars


By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality


I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?” There is no easy answer. There are several common indicators used in the industry such as coverage and bug curve. While they are absolutely necessary, these are not enough to reach the ... » read more

Shifting The Design Paradigm To Improve Verification Efficiency


We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Comparing Formal And Simulation Code Coverage


There is a difference in semantics between code coverage generated from a simulator engine and code coverage generated from a formal engine. This paper seeks to raise the awareness of verification engineers on how best to make use of the code coverage data generated by different verification engines. The paper lays out the reasons for using code coverage and describes how simulation code covera... » read more

Verifying Side-Channel Security Pre-Silicon


As security grows in importance, side-channel attacks pose a unique challenge because they rely on physical phenomena that aren’t always modeled for the design verification process. While everything can be hacked, the goal is to make it so difficult that an attacker concludes it isn't worth the effort. For side-channel attacks, the pre-silicon design is the best place to address any known ... » read more

Bug Hunt! Spiraling In On Formal Coverage Closure


By Mark Eslinger and Jin Hou Many companies have used formal verification to verify complex SoCs and safety-critical designs. Using formal verification to confirm design functionalities and to uncover functional bugs is emerging as an efficient verification approach. Although formal verification will not handle the complexity of a design at the SoC level, it is an efficient tool to verify th... » read more

Leveraging Symbolic Simulations For IO Verification


IO libraries and interface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. Interface IPs are the literal gatekeepers to the flow of logical and electrical information from one IC to another to form today’s complex computer systems, influencing almost every aspect of our lives these days. Interface IPs (e... » read more

Does Your IC Security Need A Renovation?


Five years ago, I moved from Silicon Valley to Gig Harbor, Washington and bought a fixer-upper. As part of my ongoing (and extensive) home renovations, I just finished having the entire exterior redone: roof, siding, paint, masonry, front porch, back deck, outdoor lighting, the works. If you’ve ever embarked on any kind of home remodel project, I don’t have to tell you that the process incl... » read more

Formally Verifying SystemC/C++ Designs


We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

Lower Power Chips: What To Watch Out For


Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

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