Why Your NoC Verification Strategy Must Consider Using Formal


By Ashish Darbari and Bing Xue It’d be inconceivable these days to design a modern high-performance SoC without a network-on-chip (NoC) fabric. AI hyperscalers are inherently multi-threaded and rely on using hundreds of processing elements (PEs). Crossbar-based fabric would just not scale. What also changes with the adoption of the NoC is how to handle coherency between PEs. ACE is no long... » read more

Leveraging Agentic AI Techniques to Improve Formal Verification (Infineon, et al.)


A new technical paper, "Agentic AI-based Coverage Closure for Formal Verification," was published by researchers at Infineon and the NIT Jalandhar. Abstract "Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines.... » read more

Why Proof Convergence Matters


Achieving a deterministic "yes or no" answer in semiconductor verification is becoming more challenging as chip complexity increases. There are more cores, more potential interactions, and more reliance on AI to build AI chips. Ashish Darbari, CEO of Axiomise, talks about the impact of functional interactions involving safety and security, and where to look for common patterns to prevent bugs f... » read more

Extending Formal Verification to Sequential Circuits (U. of Bremen)


Researchers from University of Bremen have released “Linear Formal Verification of Sequential Circuits using Weighted-AIGs”. Abstract "Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verifica... » read more

Formal Verification First: How AI Supports But Cannot Replace It


At a recent VLSI-D panel, industry leaders explored one of the most pressing topics in silicon design today — the intersection of AI-powered EDA, which is revolutionizing chip design for tomorrow. Ashish Darbari, CEO of Axiomise, questioned the panelists on the role of AI in chip design, optimizing PPA, validation and verification. While the panel explored the role of AI in design implemen... » read more

Formal Verification Fundamentals Remain Non-Negotiable In The New Verification Revolution


The semiconductor industry stands at a critical juncture. First-time silicon success rates have reached all-time lows, while design complexity continues to grow exponentially. System-on-chip designs now integrate billions of transistors, multiple processor cores, complex memory hierarchies, and sophisticated interconnect fabrics. In this environment, the stakes for verification accuracy have ne... » read more

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL


High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Verification and Reliability Methods For RRAM-Based Computing-in-Memory (Univ. of Bremen et al)


A new technical paper titled "Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory" was published by researchers at University of Bremen, DFKI GmbH, University of Florida and TU Munich. Abstract "Computing-in-memory (CIM) has gained immense traction owing to the benefits it provides in power, performance, and area. CIM can be don... » read more

The Future For Formal Verification


Experts at the table: Semiconductor Engineering sat down to discuss possible future directions for formal verification technology with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemen... » read more

Formal Verification’s Value Grows


Experts at the table: Semiconductor Engineering sat down to discuss why formal verification is becoming more important, with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA. Wha... » read more

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