tag: formal verification

Here At Last! Automated Verification Of Heterogeneous 2D/3D Package Connectivity
By Michael Walsh - 25 Jul, 2024 - Comments: 0

By Michael Walsh and Jin Hou with Todd Burkholder The heterogeneous integration of multiple ICs in a single package along with high-performance, high-bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making i... » read more

Changes In Formal Verification
By Ed Sperling - 11 Jul, 2024 - Comments: 0

For the better part of two decades, formal verification was considered too difficult to use in many designs and too slow for anything but narrow bug hunting. Much has changed recently. Ashish Darbari, CEO of Axiomise, explains why formal is now essential for finding deadlocks, security holes, and Xprop issues in mission-critical, safety-critical, and AI designs, and how that will apply to chipl... » read more

Verification Tools Straining To Keep Up
By Brian Bailey - 01 Jul, 2024 - Comments: 0

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing pressures. Verification is no longer just about ensuring that functionality is faithfully represented in an implementation. That alone is an insolvable task, but verification has taken on many new re... » read more

RISC-V Verification: From Simulation To Formal
By Ashish Darbari - 27 Jun, 2024 - Comments: 0

Axiomise's Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a design and how formal verification can help with bug hunting for corner-case bugs and exhaustive proofs of bug absence. » read more

Navigating The Future Of EDA
By Anika Sunda - 27 Jun, 2024 - Comments: 0

The landscape of electronic design automation (EDA) is undergoing a monumental transformation. The catalysts? Artificial Intelligence (AI) and Machine Learning (ML). These technological marvels are not just reshaping how we approach design and verification in electronics; they are redefining the possibilities within the field. Our latest podcast episode delved deep into this topic, uncovering t... » read more

Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors
By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core” was published by researchers at University of Southampton. Abstract: "Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also calle... » read more

A Unified Solution for End-to-End Low Power Verification
By Synopsys - 29 May, 2024 - Comments: 0

Low power designs are becoming increasingly prevalent in modern electronic systems, driven by the need for energy-efficient devices. Ensuring the correctness of these designs is paramount, as even minor errors can lead to catastrophic consequences. To achieve verification closure for low power designs, a combination of static verification, dynamic simulation-based verification, formal verificat... » read more

Dealing With AI/ML Uncertainty
By Karen Heyman - 25 Apr, 2024 - Comments: 0

Despite their widespread popularity, large language models (LLMs) have several well-known design issues, the most notorious being hallucinations, in which an LLM tries to pass off its statistics-based concoctions as real-world facts. Hallucinations are examples of a fundamental, underlying issue with LLMs. The inner workings of LLMs, as well as other deep neural nets (DNNs), are only partly kno... » read more

Challenges In RISC-V Verification
By Ed Sperling - 02 Apr, 2024 - Comments: 0

Designing a single-core RISC-V processor is relatively easy, but verifying it and debugging it is a different story. And it all becomes more complicated when multiple cores are involved, and when those cores need to be cache-coherent. Ashish Darbari, CEO of Axiomise, talks with Semiconductor Engineering about using assertions and formal verification technology to find bugs and prove coherency i... » read more

Verifying Hardware CWEs in RTL Designs Generated by GenAI
By Technical Paper Link - 27 Mar, 2024 - Comments: 0

A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more

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