tag: formal verification

Advances In Formal Verification Technology
By Brian Bailey - 30 Oct, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Statistical Model Checking As An Evaluation Tool of Microarchitectural Side Channels (Duke, Harvard, Univ. of Florida)
By Technical Paper Link - 17 Oct, 2025 - Comments: 0

A new technical paper titled "Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking" was published by researchers at Duke University, Harvard University and University of Florida. Abstract "Rigorous quantitative evaluation of microarchitectural side channels is challenging for two reasons. First, the processors, attacks, and defenses often exhibit probabili... » read more

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

A Balanced Approach To Verification
By Brian Bailey - 29 May, 2025 - Comments: 1

First-time chip success rates are dropping, primarily due to increased complexity and attempts to cut costs. That means management must take a close look at their verification strategies to determine if they are maximizing the potential of their tools and staff. Using simulation to demonstrate that a design exhibits a required behavior has been the cornerstone of functional verification sinc... » read more

How To Optimize Silicon Utilization To Improve PPA
By Ashish Darbari - 29 Apr, 2025 - Comments: 0

In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce ... » read more

New Ways To Improve EDA Productivity
By Ann Mutschler - 24 Apr, 2025 - Comments: 0

EDA vendors are taking aim at new ways to improve the productivity of design and verification engineers, who are struggling to keep pace with exponential increases in chip complexity in tight time-to-market windows and with constrained engineering talent pipelines. In the past, progress often was as straightforward as improving algorithms or parallelizing computations in a linear flow. But w... » read more

Easier Assertion Development And Debug With Simulation Replay
By Vin Liao - 13 Mar, 2025 - Comments: 0

By Vin Liao and Robert Ruiz Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of design intent, specifying how the design should behave—and not behave—under specified conditions. They range from simple statements, for example, that a multi-bit... » read more

Scenario Coverage In Formal Verification
By Ed Sperling - 05 Mar, 2025 - Comments: 0

A rapid increase in complexity with heterogeneous assemblies and advanced-node chips is raising all sorts of questions on the formal verification side about the completeness of coverage. Engineers may assume proofs are complete, but in many cases they're black boxes that provide little or no insights into what's actually being proven. This is where scenario coverage comes into play. Ashish Darb... » read more

Benchmark and Evaluation Framework For Characterizing LLM Performance In Formal Verification (UC Berkeley, Nvidia)
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware" was published by researchers at UC Berkeley and NVIDIA. Abstract "The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital chip design. In particula... » read more

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