Creating IP In The Shadow Of ISO 26262


On many levels, designing IP for the automotive sector is similar to targeting aerospace or medical devices — human lives are at risk if something goes wrong, and the list of regulations is significant. In practice, it can turn an interesting chip design project into a complex and often frustrating checklist exercise. In the case of ISO 26262, that includes a 12-part standard for automotiv... » read more

Design IP


Cadence is a leader in semiconductor IP addressing hyperscale computing, enterprise, data center, automotive, and artificial intelligence/machine learning (AI/ML) applications. Our IP are available in advanced-process nodes ranging from 28nm to 3nm—all silicon verified in leading-edge foundry processes. Our memory IP portfolio spans DDR, LPDDR, and GDDR. The Cadence® IP family for PCI Expres... » read more

Enablers And Barriers For Connecting Diverse Data


More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification


We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Experts At The Table: Next-Generation IP Landscape


By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more