Key Resources:
- Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
- Chiplet Fundamentals For Engineers: 2026 eBook: A 65-page in-depth research report on the next phase of device scaling.
Key Resources:
Multiple chips arranged in a planar or stacked configuration with an interposer for communication.
Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.
But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device-the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.
Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry's first 3D NAND device. Samsung's V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.
In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.
In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.
One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung's V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung's 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.
The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition.
Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.
Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.
Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a “macaroni channel,” according to Objective Analysis.
Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.
Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step-staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.
Transistors where source and drain are added as fins of the gate.
2.5D and 3D forms of integration
Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.
We start with schematics and end with ESL
Important events in the history of logic simulation
Early development associated with logic synthesis
Commonly and not-so-commonly used acronyms.
The following is a list of acronyms and what they stand for:
ACK - Acknowledge
ADC - Analog to Digital Converter
AI - Artificial Intelligence
ALD - Atomic Layer Deposition
ALE - Atomic Layer Etch
AMOLED - Active-Matrix OLED
AMP - Asymmetric Multi Processing
AOI - Automated Optical Inspection
AP - Access Point
ASIC - Application Specific Integrated Circuit
ATE - Automatic Test Equipment
BEOL - Back-End-Of-Line
BGA - Ball Grid Array
BSA - Basic Service Area
BTI - Bias-Temperature Instability
CA - Collision Avoidance
CBRAM - Conductive Bridging RAM
CCI - Cache Coherent Interconnect
CD Collision Detection
CF - Contention-Free
CFP - Contention-Free Period
CP - Contention Period
CPU - Central Processing Unit
CRC - Cyclic Redundancy Check
CSMA - Carrier Sense, Multiple Access
CFD - Computational Fluid Dynamic
CMOS - Complementary Metal Oxide Semiconductor
CNN - Convolutional Neural Network
CPP - Contacted Poly Pitch
CSP - Chip Scale Packaging
CTS - Clear To Send
DAC - Digital to Analog Convertor
DARPA - Defense Advanced Research Projects Agency
DCF - Distributed Coordination Function
DDR - Double Data Rate
DFA - Differential Fault Analysis
DFT - Design for Test
DFM - Design for Manufacturing
DIFS - Distributed Inter-frame Space
DPA - Differential Power Analysis
DL - Deep Learning
DRAM - Dynamic Random Access Memory
DRC - Design Rule Checker
DSA - Directed Self Assembly
DSP - Digital Signal Processor
DUT - Design Under Test
DUV - Design Under Verification
DVFS - Dynamic Voltage and Frequency Scaling
ECO - Engineering Change Order
EDA - Electronic Design Automation
EM - Electromagnetic
EM - Electromigration
ESL - Electronic System Level
EUV - Extreme Ultraviolet
FD-SOI - Fully Depleted Silicon on Insulator
FEOL - Front-End-Of-Line
FET - Field Effect Transistor
FIFO - First In First Out
FPGA - Field Programmable Gate Array
GAA - Gate-All-Around
GaAs - Gallium Arsenide
GaN - Gallium Nitride
GPU - Graphics Processing Unit
HBM - High Bandwidth Memory
HBT - Heterojunction Bipolar Transistor
HDL - Hardware Description Language
HMC - Hybrid Memory Cube
IC - Integrated Circuit
IEEE - Institute of Electrical and Electronics Engineers
IIC - Industrial Internet Consortium
IIoT - Industrial Internet of Things
IoT - Internet of Things
IP - Intellectual Property
IR - Infra-red
ISM - Industrial, Scientific, Medical
ISS - Instruction Set Simulator
ILT - Inverse Lithography Technology
JTAG - Joint Test Action Group
LAN - Local Area Network
LCD - Liquid Crystal Display
LTE - Long-Term Evolution
MAC -Media Access Control
MCU - Microcontroller
MEMS - Micro Electrical Mechanical Systems
MES - Manufacturing Execution Systems
ML-Machine Learning
MOL - Middle-Of-Line
MRAM - Magnetic Random Access Memory
NA - Numerical Aperture
NGL - Next-Generation Lithography
NIC - Network Interface Card
NSF - National Science Foundation
NVM - Non-Volatile Memory
OCAP - Out of Control Action Plan
OLED - Organic Light-Emitting Diode
OPC - Optical Proximity Correction
OS - Operating System
OSAT - Outsourced Semiconductor Assembly and Test
OTP - One Time Programmable
PCB - Printed Circuit Board
PCF - Point Coordination Function
PCM - Phase-Change Memory
PDK - Process Design Kit
PDN - Power Delivery Network
PHY - Physical Layer
PI - Power Integrity
PIFS - Point Inter-frame Space
PnR - Place and Route
PoP - Package-on-Package
PPA - Power, Performance, Area
PPAC - Power, Performance, Area, Cost
PRNG - Pure Random Number Generator
PVT - Process, Voltage, Temperature
RAM - Random Access Memory
RC4 - Rivest Cipher 4
RDL - Register Definition Language
RDL - Redistribution Layer
RF - Radio Frequency
ROM - Read Only Memory
RoT - Root Of Trust
RTL - Register Transfer Level
RTOS - Real Time Operating System
RTS - Request To Send
SCM - Storage Class Memory
SerDes - Serializer / Deserializer
SIFS - Short Inter-frame Space
SI - Signal Integrity
SiC - Silicon Carbide
SiGe - Silicon Germanium
SK - Shared Key
SMP - Symmetric Multi Processing
SoC - System on Chip
SOI - Silicon on Insulator
SPA - Simple Power Analysis
SRAF - Sub-Resolution Assist Features
SRAM - Static Random Access Memory
SSD - Solid-state Storage Drives
SSID - Service Set Identifier
STA - Static Timing Analysis
STI - Shallow Trench Isolation
TLM - Transaction Level Model
TSV - Through Silicon Via
UPF - Unified Power Format
USB - Universal Serial Bus
UVM - Universal Verification Methodology
VHDL - VHSIC Hardware Description Language
VHSIC - Very High Speed Integrated Circuit
VSLI - Very Large Scale Integration
VIP - Verification Intellectual Property
VoWi-Fi - Voice over Wi-Fi
Vt - theshold Voltage
Wan - Wide Area Network
WEP - Wired Equivalency Protocol
Wi-Fi - Wireless High Fidelity
WiGIG - Gigabit Wi-Fi
WLAN - Wireless Local Area Network
WLP - Wafer Level Packaging
WPA - Wi-Fi Protected Access
Sensing and processing to make driving safer.
Advanced packaging is a general grouping of a variety of distinct techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package.
While putting multiple chips in a package has been around for decades, the driver for advanced packaging is directly correlated with Moore's Law. Wires are shrinking along with transistors, and the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, interposers, bridges or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals can be reduced. Moreover, depending on the package, there are fewer physical effects to contend with and components developed at different process nodes can be mixed.
These approaches are now in use across a wide range of products, but initial concerns about cost and time to market continue to slow adoption. That is changing. EDA companies have introduced new tools and flows to automate advanced packaging, and both foundries and OSATs are refining the processes to make it more predictable and less expensive. That is getting a boost by the rising cost of scaling transistors beyond 28nm, as well.
An approach to software development focusing on continual delivery and flexibility to changing requirements
How Agile applies to the development of hardware systems
A way of improving the insulation between various components in a semiconductor by creating empty space.
The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.
Semiconductors that measure real-world conditions
Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.
The design and verification of analog components.
A custom, purpose-built integrated circuit made for a specific task or product.
An IC created and optimized for a market and sold to multiple companies.
Using machines to make decisions based upon stored knowledge and sensory input.
Code that looks for violations of a property
A method of measuring the surface structures down to the angstrom level.
A method of depositing materials and films in exact places on a surface.
ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.
The generation of tests that can be used for functional or manufacturing verification
Issues dealing with the development of automotive electronics.
Time sensitive networking puts real time into automotive Ethernet.
Noise in reverse biased junctions
Verification methodology created by Mentor
IC manufacturing processes where interconnects are made.
Devices that chemically store energy.
Transformation of a design described in a high-level of abstraction to RTL
A reverse force to electromigration.
Also known as Bluetooth 4.0, an extension of the short-range wireless protocol for low energy applications.
Transistor model
On-chip logic to test a design.
Chiplet interconnect specification.
Interface model between testbench and device under test
C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.
Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.
CD-SEM, or critical-dimension scanning electron microscope, is a tool for measuring feature dimensions on a photomask.
Making CDC interfaces predictable
The CPU is an dedicated integrated circuit or IP core that processes logic and math.
A lab that wrks with R&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.
Testbench component that verifies results
A process used to develop thin films and polymer coatings.
Design is the process of producing an implementation from a conceptual form
The design, verification, implementation and test of electronics systems into integrated circuits.
Exchange of thermal design information for 3D ICs
A chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function, using the node best suited to the function. The chiplet concept is often referred to as the disaggregation of the system on chip (SoC), using heterogeneous integration techniques to put multiple die or chiplets into a system in package (SiP) or other advanced packaging concept. The technology is still nascent and presents many issues for design, test, manufacturing, and integration teams to work out.
There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.
With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.
A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system.
Commercial vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandou’s chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandou’s interconnect technology.
DARPA’s approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.
The CHIPS program started in 2017. The program has various types of contractors/sub-contractors—manufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).
Asynchronous communications across boundaries
Dynamic power reduction by gating the clock
Design of clock trees for power reduction
Complementary metal-oxide semiconductor (CMOS) is a fabrication technology for semiconductor systems that can be used for the construction of digital circuitry, memories and some analog circuits. The technology is based on the pairing of two metal oxide semiconductor field effect transistors (MOSFET), one of which is a p-type and the other an n-type transistor. The term metal oxide semiconductor is a reference to the traditional structure of the device where there would be a metal gate on top of an oxide layer on top of a semiconductor. Today, the metal layer is replaced by a polysilicon layer most of the time.
CMOS dissipates power in two primary ways. When they are switching, there is a momentary short circuit across the transistor pair. Also, switching has to dissipate any stored charge (load capacitance) on the electrical connector between it and any other switches connected to it within the circuit. This is referred to as dynamic power. For older geometries, this was the majority of the power consumed by such devices. In more modern devices, the second power draw, when the device is remaining in the same state, has become more important. This is leakage power and may be a significant percentage of total power consumption.
Metrics related to about of code executed in functional verification
Verify functionality between registers remains unchanged after a transformation
Faster form for logic simulation
Complementary FET, a new type of vertical transistor.
Combinations of semiconductor materials.
Interconnect between CPU and accelerators.
The structure that connects a transistor with the first layer of copper interconnects.
A technique for computer vision based on machine learning.
Completion metrics for functional verification
Interference between signals
Crypto processors are specialized processors that execute cryptographic algorithms within hardware.
A method of conserving power in ICs by powering down segments of a chip when they are not in use.
Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.
How semiconductors are sorted and tested before and after implementation of the chip in a system.
The plumbing on chip, among chips and between devices, that sends bits of data and manages that data.
The removal of bugs from a design
Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.
An observation that as features shrink, so does power consumption.
Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.
Techniques that reduce the difficulty and cost associated with testing an integrated circuit.
Protection for the ornamental design of an item
A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer
Locating design rules using pattern matching techniques.
Sources of noise in devices
Insertion of test logic for clock-gating
A wide-bandgap synthetic material.
Categorization of digital IP
A digital signal processor is a processor optimized to process signals.
A digital representation of a product or system.
A complementary lithography technology.
DNA analysis is based upon unique DNA sequencing.
A patterning technique using multiple passes of a laser.
Colored and colorless flows for double patterning
Dynamic random access memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared with six transistors in SRAM. This allows DRAM to reach very high density.
Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.
In today's systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.
DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.
Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.
The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.
Several types of DRAM were being developed in the early 2000's that used characteristics of silicon on insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) were being developed by Renesas and the Z-RAM Zero capacitor RAM by the now defunct company Innovative Silicon (Micron owns its patents). Improvements in SRAM manufacturing negated any benefits of these
The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.
Dynamically adjusting voltage and frequency for power reduction
Hardware Verification Language
A slower method for finding smaller defects.
Lithography using a single beam e-beam tool
The difference between the intended and the printed features of an IC layout.
Electromigration (EM) due to power densities
Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.
Levels of abstraction higher than RTL used for design and verification
Transfer of electrostatic charge.
An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.
Special purpose hardware used for logic verification
Capturing energy from the environment
Noise caused by the environment
A method for growing or depositing mono crystalline films on a substrate.
Reuse methodology based on the e language
Methods for detecting and correcting errors.
Ethernet is a reliable, open standard for connecting devices by wire.
EUV lithography is a soft X-ray technology.
Finding out what went wrong in semiconductor design and manufacturing.
A way of including more features that normally would be on a printed circuit board inside a package.
Evaluation of a design under the presence of manufacturing defects
Ferroelectric FET is a new type of memory.
Reprogrammable logic device
A three-dimensional transistor.
Flash memory is a modern form of erasable memory. Whereas EEPROM was erased in bulk, flash allows more selective erasure.
The concept was developed by Dr. Fujio Masuoka of Toshiba. It was presented at the 1984 IEEE International Electron Devices Meeting, IEDM held in San Francisco, California. Intel introduced the NOR chip in 1988; Toshiba introduced the NAND type chip in 1991.
Most commercially available flash products are guaranteed to withstand between 100,000 and 1,000,000 program/erase cycles.
With NOR flash, the memory cells are connected in parallel enabling the device to have better random access. NAND flash is optimized for density and access is performed in a serial manner. This reduces the amount of access circuitry required. For this reason NOR has traditionally been used for code access and NAND for data access.
Integrated circuits on a flexible substrate
An automotive communications protocol
Noise related to resistance fluctuation
A type of interconnect using solder balls or microbumps.
A transistor type with integrated nFET and pFET.
Formal verification involves a mathematical proof to show that a design adheres to a property
A company that specializes in manufacturing semiconductor devices.
Coverage metric used to indicate progress in verifying functionality
Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.
Functional verification is used to determine if a design, or unit of a design, conforms to its specification.
GaN is a III-V material with a wide bandgap.
A transistor design with a gate is placed on all four sides of the channel.
Power reduction techniques available at the gate level.
noise related to generation-recombination
A neural network framework that can generate new data.
Germany is known for its automotive industry and industrial machinery.
Graphene is two dimensional allotrope of carbon in which carbon atoms are arranged in a hexagonal pattern in a single, one atom thick layer. It is widely credited as spurring research into many other 2D materials.
The material had been theorized and observed on surfaces for decades, but in 2004 graphene was isolated and characterized by Andre Geim and Kostya Novoselov at the University of Manchester, research that earned them the 2010 Nobel Prize in Physics. The researchers used sticky tape to remove flakes from bulk graphite then repeatedly separated the flakes.
Graphene has no band gap and conducts electricity extremely well, with electron mobility at room temperature reported to be over 15000 cm2⋅V−1⋅s−1. Thermal conductivity is high, and the material is also nearly transparent and around 100 times stronger than steel in proportion to its thickness.
While graphene and other 2D materials can be isolated in small quantities in research environments using mechanical exfoliation (the sticky tape method), making it on a commercial level is more difficult. One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.
An electronic circuit designed to handle graphics and video.
Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.
Fully designed hardware IP block
Use of special purpose hardware to accelerate verification
Historical solution that used real chips in the simulation process
Optimizing the design by using a single language to describe hardware and software.
Power creates heat and heat affects power
The process of integrating different chips, chiplets, and chip components into packages.
A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging.
An umbrella term (circa 2015) for advanced packaging in semiconductors.
Synthesis technology that transforms an untimed behavioral description into RTL
Defines a set of functionality and features for HSA hardware
Runtime capabilities for the HSA architecture
What are the types of integrated circuits?
Hardware Description Language
Analog extensions to VHDL
A collection of VHDL 1076.1 packages
Modeling of macro-cells in VHDL
Boundry Scan Test
IEEE ratified version of Verilog
Standard for Verilog Register Transfer Level Synthesis
Extension to 1149.1 for complex device programming
Functional verification language
SystemC
Standard for integration of IP in System-on-Chip
IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device
IEEE ratified version of SystemVerilog
Universal Verification Methodology
IEEE Standard for Design and Verification of Low-Power Integrated Circuits also known by its Accellera name of Unified Power Format (UPF)
Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
Verification language based on formal specification of behavior
IEEE 802.1 is the standard and working group for higher layer LAN protocols.
IEEE 802.11 working group manages the standards for wireless local area networks (LANs).
IEEE 802.15 is the working group for Wireless Specialty Networks (WSN), which are used in IoT, wearables and autonomous vehicles.
"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.
Standards for coexistence between wireless standards of unlicensed devices.
IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.
Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems
Power Modeling Standard for Enabling System Level Analysis
Specific requirements and special consideration for the Internet of Things within an Industrial setting.
Wafer costs across nodes
Power optimization techniques for physical implementation
Performing functions directly in the fabric of memory.
Thermal noise within a channel
IGBTs are combinations of MOSFETs and bipolar transistors.
Integration of multiple devices onto a single piece of semiconductor
A semiconductor company that designs, manufactures, and sells integrated circuits (ICs).
A design or verification unit that is pre-packed and available for licensing.
Method to ascertain the validity of one or more claims of a patent
Buses, NoCs and other forms of connection between various elements in an integrated circuit.
Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.
Fast, low-power inter-die conduits for 2.5D electrical signals.
Finding ideal shapes to use on a photomask.
Injection of critical dopants during the semiconductor manufacturing process.
Standard for integration of IP in System-on-Chip
The voltage drop when current flows through a resistor.
Standard related to the safety of electrical and electronic systems within a car
Standard to ensure proper operation of automotive situational awareness systems.
A standard (under development) for automotive cybersecurity.
The energy efficiency of computers doubles roughly every 18 months.
Languages are used to create models
Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.
Device and connectivity comparisons between the layout and the schematic
Cells used to match voltages across voltage islands
Deviation of a feature edge from ideal shape.
Removal of non-portable or suspicious code
LELE is a form of double patterning
A type of double patterning.
Light used to transfer a pattern from a photomask onto a substrate.
Coefficient related to the difficulty of the lithography process
Correctly sizing logic elements
Restructuring of logic for power reduction
A simulator is a software process used to execute a model of hardware
Methodologies used to reduce power consumption.
Verification of power circuitry
An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.
Uses magnetic properties to store data
Observation related to the amount of custom and standard content in electronics.
Tracking a wafer through the fab.
Noise sources in manufacturing
Semiconductor materials enable electronic circuits to be constructed.
A semiconductor device capable of retaining state information for a defined period of time.
Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.
A key tool for LED production.
Unstable state within a latch
Observation that relates network value being proportional to the square of users
Describes the process to create a product
Metrology is the science of measuring and characterizing tiny structures and materials.
A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.
The integrated circuit that first put a central processing unit on one chip of silicon.
The integration of analog and digital.
Models are abstractions of devices
A midrange packaging option that offers lower density than fan-outs.
A way of stacking transistors inside a single chip instead of a package.
Observation related to the growth of semiconductors by Gordon Moore.
An advanced form of e-beam lithography
An early approach to bundling multiple functions into a single package.
Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.
Use of multi-threshold voltage devices
A way to image IC designs at 20nm and below.
A hot embossing process type of lithography.
A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.
Optimizing power by computing below the minimum operating voltage.
Moving compute closer to memory to reduce access costs.
NBTI is a shift in threshold voltage with applied stress.
An in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them.
A method of collecting data from the physical world that mimics the human brain.
A compute architecture modeled on the human brain.
Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.
Random fluctuations in voltage or current on a signal.
Memory in which information is retained even when a power source is not present.
Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM's capacity is hard to scale at smaller geometries, and it needs higher voltages to program the cells. More die area may be needed to support capacities required by the additional processing cores at finer process geometries, and additional manufacturing cost may be required to support higher voltages.1
NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the process node, the voltage, the type of NVM and what’s being stored in it, as well as the overall chip or system budget. It is a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.
Fundamentally, there are two types of NVM:
Multi-time programmable (MTP) NVM can be programmed many times.
One-time programmable (OTP) NVM can be programmed once.
Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Because they can be manufactured using a standard CMOS process, these MTP NVMs can continue to be scaled, but they require a floating gate, like a flash cell. A charge is trapped on a floating gate.
Then there’s the regular gate and the transistor. When you erase it, you remove the charge from the floating gate. Also, this floating gate requires a thicker oxide, and not all processes offer that. This is why MTP scaling basically stopped at 40nm and 28nm. Beyond that, it’s difficult to do it because the oxide thickness is not there to do to make it happen.
However, if NVM could be embedded in the same logic process without having to make tweaks to the process, then the costs are more manageable, and this is exactly what Synopsys was after with its acquisition of Sidense and Kilopass, both of which developed versions of OTP NVM.
The OTP technology doesn’t require the thicker oxide that is required for the MTP, and there is no floating gate.
1 MUTSCHLER, Ann. "Non-Volatile Memory Tradeoffs Intensify," Semiconductor Engineering, JANUARY 22ND, 2020, https://semiengineering.com/non-volatile-memory-tradeoffs-intensify/
Verification methodology created from URM and AVM
Disabling datapath computation when not enabled
Method used to find defects on a wafer.
A way to improve wafer printability by modifying mask patterns.
The company that buys raw goods, including electronics and chips, to make a product.
Companies who perform IC packaging and testing - often referred to as OSAT
The ability of a lithography scanner to align and print various layers accurately on top of each other.
How semiconductors get assembled and packaged.
Outlier detection for a single measurement, a requirement for automotive electronics.
High-speed serial expansion bus for connecting sending data between devices.
A thin membrane that prevents a photomask from being contaminated.
Memory that stores information in the amorphous and crystalline phases.
A template of what will be printed on a wafer.
Light-sensitive material used to form a pattern on the substrate.
Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.
Physically connects devices and is the conduit that encodes, decodes bits of data.
PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering.
Making sure a design layout works as intended.
A set of unique features that can be built into a chip but not cloned.
Lowering capacitive loads on logic
Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.
Components of power consumption
Power domain shutdown and startup
Definitions of terms related to power
Moving power around a device.
How is power consumption estimated
Reducing power by turning off parts of a design
Special flop or latch used to retain the state of the cell when its main power supply is shut off.
Addition of isolation cells around power islands
Power reduction at the architectural level
Ensuring power control circuitry is fully verified
An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.
A power semiconductor used to control and convert electric power.
A power IC is used as a switch or rectifier in high voltage power applications.
Noise transmitted through the power delivery network
Controlling power for power shutoff
Techniques that analyze and optimize power in a design
Fundamental tradeoffs made in semiconductor design for power, performance and area.
The design, verification, assembly and test of printed circuit boards
power optimization techniques at the process level
Variability in the semiconductor manufacturing process
A measurement of the amount of time processor core(s) are actively in use.
An integrated circuit or part of an IC that does logic and math processing.
Verification language based on formal specification of behavior
A different way of processing data using qubits.
Issues that pertain to Radio Frequency (RF) analog
Random trapping of charge carriers
The process of rapidly heating wafers.
Copper metal interconnects that electrically connect one part of a package to another.
Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.
Memory utilizing resistive hysteresis
Synonymous with photomask.
A proposed test data standard aimed at reducing the burden for test engineers and test operations.
An open-source ISA used in designing integrated circuits at lower cost.
Trusted environment for secure functions.
An abstraction for defining the digital portions of a design
Optimization of power consumption at the Register Transfer Level
A series of requirements that must be met before moving past the RTL phase
Verification methodology based on Vera
Algorithm used to solve problems
Additional logic that connects registers into a shift register or scan chain for increased test efficiency.
Mechanism for storing stimulus in testbench
Testbench support for SystemC
A form of double patterning.
Subjects related to the manufacture of semiconductors
Methods and technologies for keeping data safe.
Combining input from multiple sensor types.
An IC that conditions an analog sensor signal and converts to it digital before sending to a microcontroller.
Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.
A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.
In semiconductor development flow, tasks once performed sequentially must now be done concurrently.
When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.
Quantization noise
A class of attacks on a device and its contents by analyzing information using different access methods.
Undetected errors in data output from an integrated circuit.
A wide-bandgap technology used for FETs and MOSFETs for power transistors.
The integration of photonic devices into silicon
A simulator exercises of model of hardware
Special purpose hardware used to accelerate the simulation process.
Disturbance in ground voltage
Synthesizable IP block
Verification methodology utilizing embedded processors
Defines an architecture description useful for software design
Circuit Simulator first developed in the 70s
A type of neural network that attempts to more closely model the brain.
A type of MRAM with separate paths for write and read.
A patent that has been deemed necessary to implement a standard.
The most commonly used data format for semiconductor test information.
Standards are important in any industry.
SRAM is a volatile memory that does not require refresh
Constraints on the input to guide random generation process
Random variables that cause defects on chips during EUV lithography.
An advanced type of MRAM
Use of Substrate Biasing
Coupling through the substrate.
A method for bundling multiple ICs to work together as a single chip.
A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor
A class library built on top of the C++ language used for modeling hardware
Analog and mixed-signal extensions to SystemC
Industry standard design and verification language
Google-designed ASIC processing unit for machine learning that works with TensorFlow ecosystem.
Software used to functionally verify a design
Noise related to heat
Through-Silicon Vias are a technology to connect various die in a stacked die configuration.
Basic building block for both analog and digital integrated circuits.
Minimizing switching times
A multi-patterning technique that will be required at 10nm and below.
A type of transistor under development that could replace finFETs in future process technologies.
Standard for safety analysis and evaluation of autonomous vehicles.
The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.
Accellera Unified Power Format (UPF)
Die-to-die interconnect specification.
Verification methodology
SystemVerilog version of eRM
Patent to protect an invention
Hardware Verification Language
A pre-packaged set of code used for verification.
A standardized way to verify integrated circuit designs.
A document that defines what functional verification is going to be performed
Hardware Description Language in use since 1984
Procedural access to Verilog objects
Analog extensions to Verilog
Hardware Description Language
An abstract model of a hardware system enabling early software execution.
Verification methodology built by Synopsys
Memory that loses storage abilities when power is removed.
Use of multiple voltages for power reduction
The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.
Verifying and testing the dies on the wafer after the manufacturing.
The science of finding defects on a silicon wafer.
A brand name for a group of wireless networking protocols and technology,
3D memory interface standard
Creating interconnects between IC and package using a thin wire.
A way of moving data without wires.
IC interconnect architecture
X Propagation causes problems
A data-driven system for monitoring and improving IC yield and reliability.
A vulnerability in a product’s hardware or software discovered by researchers or attackers that the producing company does not know about and therefore does not have a fix for yet.
