A new technical paper titled “Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity” was published by researchers at Arizona State University and University of Minnesota.
Abstract:
“The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional I/O circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and SPICE simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.”
Find the technical paper here. November 2025.
Haque, Emad, Pragnya Sudershan Nalla, Jeff Zhang, Sachin S. Sapatnekar, Chaitali Chakrabarti, and Yu Cao. “Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity.” arXiv preprint arXiv:2511.10760 (2025).
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