PCIe ATS verification; physical AI; adopting AI EDA; custom AMBA Viz plugins; V2G; fab construction workforce.
Cadence’s Anupriya K explains how Address Translation Services (ATS) acts as the fast lane for PCIe memory access by caching address translations directly on the device and what makes it one of the toughest verification problems to solve.
Synopsys’ Greg Sorber considers the economic potential of physical AI and the impact that embedding intelligence into robots, vehicles, and equipment will have on future factories, hospitals, and city streets.
Siemens’ Emma-Jane Crozier provides some tips for getting started with using AI in EDA, including identifying the biggest pain points for your team, adopting it with a specific flow or goal in mind first, working closely with the vendor, and measuring the impact to share with other teams.
Arm’s Tony Nip shares how to create AMBA Viz plugins with custom hardware signal, bus, and event analysis for more flexible RTL debug and performance analysis.
Keysight’s Andrew Cifala finds that achieving the promise of vehicle-to-grid technology will require end-to-end interoperability and a shared test environment across utilities, EV OEMs, charging providers, and other stakeholders.
Skanska’s Joycelyn Yue cautions that semiconductor fab buildout could be hampered by a shortage of qualified construction tradespeople, particularly in critical disciplines like electrical and mechanical work, where there’s a generational gap in the workforce.
Plus, don’t miss the blogs featured in the latest Low Power-High Performance newsletter:
Siemens EDA’s Emma-Jane Crozier illustrates the challenges facing AI agents in solving specific problems in the context of generic frameworks.
Rambus’ Paul Karazuba explains how LPDDR characteristics once primarily associated with extending smartphone battery life map directly onto the needs of real-time on-device inference.
Cadence’s Sandeep Grover digs into UALink verification and what that entails.
Arm’s Satadal Bhattacharjee explains why CPUs are needed for agentic AI workloads.
Synopsys’ Sumit Vishwakarma outlines how low-latency fabrics, topology-aware scheduling, and tiered memory bring compute closer to data and reduce coordination overhead.
Quadric’s Marc Meszaros shows the benefits of recompiling and re-profiling the entire model zoo across a broad sweep of hardware configurations.
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