Where AI will be successful, who will benefit, and how that will affect the design process?
Key Takeaways:
Semiconductor Engineering sat down to discuss how AI will alter chip design, where it will be successful, how AI agents will be managed, and who will oversee them, with Cindy Cui, vice president of global customer success at ChipAgents; Wally Rhines, CEO of Silvaco; Shelly Henry, CEO of Moores Lab AI; Dave Kelf, CEO of Breker Verification Systems; Vince Wong, head of AI development at Verific; and Ann Wu, CEO of Silimate. This panel discussion was held in front of a live audience at the recent 2026 ESD Alliance Executive Outlook meeting. To view part one of this discussion, click here.
L-R: Breker’s Kelf; Silvaco’s Rhines; Verific’s Wong; Moores Lab AI’s Henry; Silimate’s Wu; ChipAgents’ Cui. Photo Credit: Paul Cohen, SEMI ESDA
SE: There are two major issues with AI chips. One is knowing where a chip is going to be used and what the workload will be. The second is that the more successful agentic AI becomes, the less likely engineers will be able to say, ‘This is wrong.’ What are you seeing so far?
Kelf: We know that hallucinations and things like that are problematic, and that everything has to be double-checked. We do that today. We have a design flow, and we have a verification flow that checks the design flow. The question is what we need to add to that to make sure we have those checks to ensure this works properly. And what can you build in to make this 100% reliable, which is quite a big ask?
Henry: Today, the general-purpose LLMs and agentic AI frameworks that are provided by OpenAI and Anthropic and others are not geared toward the semiconductor industry. There is a missing piece. We still need semiconductor expert knowledge to say whether whatever is being done by AI is correct or not. Maybe five years from now there will be agents that will do that job, but we are not there today. We still need some supervision, and that comes from experience and an understanding of what the chip is for.
Cui: We are not yet there with one-button-click tape-out. If we have AI controlling the design of the entire chip or system all by itself, where’s the accountability? Without that, this could be very dangerous. We will still need a human engineer to make the proper judgment calls and tradeoffs and to verify the critical evidence. But eventually, we will be able to achieve a successful tape-out and send off the entire flow. That’s one area. Another is that we need to talk about building the future generation of engineers. If we make AI solutions a black box type of solution, you may address some productivity issues today, but we may create even more of a talent gap issue tomorrow. We need to continue to build engineering expertise to be able to lead the entire industry into the future.
SE: All the big chipmakers are saying they’re looking beyond a human in the loop. They’re all looking at this as a push-button technology. So now you’re one step back from where you were before. What’s the impact of that?
Kelf: You’re never going to get that. One problem we’ve had with EDA through the years is that engineers who are using EDA tools need to know what they are doing. We saw this with high-level synthesis, where these very high-level SystemC models were created, run through high-level synthesis, and magically, out came a bunch of gates. Engineers were asking, ‘How is this possible? How do they introduce the timing? What’s going on there?’ And because of that, those tools didn’t take off. They’re sort of taking off now, but it’s taken decades. So this can’t be a black-box process. It has to be pretty transparent, because the engineers who are using it have to fundamentally see, ‘Here’s what’s going on inside the tool to give me this result.’ When they get that, then they’ll start adopting and using it, getting a feel for it, and start trusting it, as well. And then we can start to see if the results actually add to that and come out correctly.
Rhines: High-level synthesis actually had its strengths and its adopters because it increased the possible solution space that could be explored. So when you do C synthesis a thousand times as fast as you could to RTL synthesis, you suddenly could explore a much larger space. Then, of course, the people moved directly to synthesized data paths, not control logic. The result was a lot of very visible companies adopted it for that reason. And I’d argue that AI is doing essentially the same thing. It’s allowing you to explore a very large solution space and look for the most viable alternatives early in the process.
SE: With high-level synthesis, though, that involved the same problem for a lot of different companies. What we’re seeing now is a lot more customization than we’ve seen before. How does that play out here, because there isn’t a precedent? And there are no economies of scale now, except for large players.
Rhines: This is a great thing. Everybody needs a custom design and custom software. This is going to generate enormous revenue for all of us. For a long time, every new generation was a standard, whether it was IBM 360 mainframes or the DEC VAX for minicomputers, or the 8086 for personal computers. And I thought, ‘Nvidia has the next generation.’ And then they come out and announce, ‘Oh, by the way, we need a totally different architecture for each algorithm in the inferencing process. And so now they’re introducing others. They acquire Groq. For AI, you need every possible ounce of performance and minimized power for every application. So this general-purpose processor thing is going out the window, and we’re seeing more and more proliferation of unique architectures, which is terrific for the EDA industry.
Wu: This is a case of Jevons Paradox, with this ability to create really specialized chips that are aligned with a particular workload. The goal, or the hope here, is that what the hyperscalers are doing will trickle down or be democratized for other players that might want to do this sort of vertical stack alignment. This goes back to two aspects we talked about earlier. On one hand, is this going to impact the number of engineers that are needed? We’re going to see some amount of split between companies with different cultures or organizational goals. There are some companies that are going to take that as, ‘Okay, we can run leaner. We can trim our headcount, maybe keep the architects or the people who call the shots.’ There are going to be other companies that say, ‘Hey, now we have more resources, so we can do more. We can pursue those aggressive opportunities that previously we weren’t able to.’ And there are going to be companies that follow the path of Apple and Amazon and Meta. ‘Hey, can I vertically optimize for my own purposes?’ That goes back to the talent issue, where ultimately what we really need to make sure of is that you have people who can do a tape-out and that there’s ownership. ‘You own this, and you are directly responsible for this block, or this subsystem, or this entire system. If it fails, that is on you as a director, as a team, as an engineer.’ That’s how silicon works, and that’s not going away. The way in which organizations are going to be able to keep doing that is to have intuition, which comes from two places. You have to have mileage and know what good looks like, and that comes with experience. And that comes back to not having that black box.
SE: Is there enough commonality in order to leverage the tools available today?
Cui: I was in traditional EDA for years, and now I’m with an AI startup. I’ve noticed there’s a totally different way to create a customized solution. A lot of engineers have become an AI-native engineering group. The younger generation of engineers can create code super quickly using all the general-purpose AI tools. For example, at ChipAgents we release a new version on a weekly basis, versus traditional EDA, where people may create a new release every six months to a year. That speed has enabled us to create even more customized solutions. All of the AI startups are trying to enable a breakthrough solution. We really need to differentiate, because we have the capability to create something really special, really breakthrough, and really new. That’s the future for specialization. We can further scale that, but not as a general-purpose tool for chip design.
SE: That’s a fundamental change for EDA, which has always been about developing tools that can be used across many designs, right?
Kelf: This is not new. If you look at a chip today, you’ve got processors, which are pretty standard. You’ve got a whole bunch of IP on it, which is pretty standard, and you’ve got two, three, or four accelerators on a big SoC, which is custom. So a lot of it is pretty generic, and we’re going more and more in that direction, and that’s not going to change.
SE: We now have chiplets, mechanical issues from going into three dimensions, and none of that is in EDA.
Kelf: But we’ve always had these evolutions going on, and so far we’ve managed to deal with it. We’ll continue to do that, and AI will help with that.
Henry: I’ve built over 18 chips. When I was working at Arm, they were building chips for the entire world. They have no idea what the workload will be on the chip, so they will throw the kitchen sink at it to verify it. That was their philosophy, and that’s what they did, and that’s what they had to do. And to be fair, they will test it on every single simulator, as well, to make sure that when it goes to their customers, it should work seamlessly. That was one extreme. And then, when I was working at Microsoft, it was slightly different. We were building chips for servers, and we knew the entire stack. It was a different team that built the software, but we still knew the stack. So even if there were some kind of issues in the chip, we could talk to the software team and say, ‘Okay, patch it.’ Or, ‘Don’t do that, then it will be fine.’ So that’s the middle one. Then there was the other extreme, when I was talking to people at Google, where they said, ‘Oh, we don’t even believe in functional coverage. We just write our code, put that under FPGA design, and if it works, we tape out the chip. That’s it.’ Those are three different extremes. So when you go more and more toward the Google style, then we might need different kinds of tools to address that because we are going very custom at that time.
Wong: The tools we have now are sufficient. It’s a matter of leveraging the AI because that’s really the brains behind it, and coming up with novel ways to make use of these tools. So, for example, you could use AI inside a tool, or you can have AI control the tool. I think the latter is the right way to go. It’s improving on its own. If you embed it inside your tool, then it’s going to be restricted. So anytime the LLMs themselves get improved, you take it out and plug in a new one. It could be three months down the line. These are free upgrades. The tools themselves have to keep on improving, and there will be more tools. And then, what we have today and what’s going to be available in the future, together with AI, should be enough to handle all these jobs.
SE: What happens when AI doesn’t do what it’s supposed to do, and when will we know that? Will there be super agents overseeing lesser agents? Are we about to get a hierarchy of agents that we didn’t have before?
Henry: When your chip breaks, you’ll know.
SE: We don’t always know that, though.
Wu: This is why we still rely on deterministic tools, sign-off tools, etc.
Kelf: There will have to be multiple flows self-checking. Today, we have a design verification flow. We’ll have the same thing, but maybe much more elaborate. Maybe it is super agents on top of agents.
Rhines: And you have other things like stochastic multi-agent consensus-building, where you get multiple agents voting on each other’s approaches and you develop a consensus, or you get verification agents whose job is to take an independent view. They’re not biased by the input you gave the original. There are lots of ways to get a diversity of viewpoints, but I agree that the bugs that are going to be a problem are the ones that don’t show up until late in the process — or worse yet, after you’re shipping product.
SE? What kinds of skills are engineers going to need to stay in the game? And what does the design and verification workforce look like in five years?
Henry: It’s very similar to what we saw in the early 2000s or late 1990s when computers became so prevalent and accountants stopped using ledgers. Accountants are still there. They use spreadsheets now. That’s the only difference. But the ones who refused to use the technology, their jobs became obsolete. If you insist on still using ledgers to write down stuff, your job is gone. All the jobs will be fine, as long as you are able to use the power of AI to increase your productivity.
Kelf: I do share this concern, though, on one point. Since we’re using AI internally, writing a lot of the core basic functions with it, it’s great. The problem is, that’s what entry-level grads do. So we’ll bring them in, they’ll write some of the basic stuff, and those are the folks that are under some pressure. They’re going to have to evolve and figure out how to use the AI tools to do that work. The problem is that we all start out as entry-level grads. So we need those people. But if we haven’t got entry-level folks building up to that, we’re going to lose that. And this is kind of a big concern.
Wu: There’s definitely a holistic embrace of AI, but with a caveat. For example, the AI systems we have today have gaps. They’ll hallucinate. They’ll come up with various things that may or may not be correct. For the users we serve, and the successful teams that I see — at least right now — one of the most useful attributes is the ability to discern. That comes from some amount of creativity and insight. A lot of the power users or the people who are adapting very well can still see the useful insights, even if the output is not 100% correct. They can still glean what is useful, and understand and bypass what is noise. And they can navigate that very effectively. The necessity of this attribute may fluctuate as AI systems become more robust over time and more correct. But with the stochastic nature of the models, having this ability to be discerning based on intuition and creativity is important.
Rhines: There’s a possibility it could be the opposite of what you said. If your new college grads come in and do grunt work — the documentation, the test programs, and all those kinds of things — those people are going to be replaced. But if I look back at when Verilog and VHDL came along and we started moving up from schematic capture, the older experienced designers said, ‘Oh, these guys don’t even understand how a transistor works. They’re just software programmers. They’re no good. We can’t use them.’ But over time, the new college graduates were the quickest to pick up Verilog. VHDL, and the 20- to 30-year-olds did it pretty fast, too. It was the 40- and 50-year-olds who never changed. So there’s the possibility that instead of obsoleting the jobs of new college grads, we obsolete the jobs of people who refuse to change.
Kelf: And instead of booing speakers at college commencements, they should be embracing it and saying, ‘Hey, how can I get involved in this? How can I figure this out? And how can I make use of it?’
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