Reticle Stitching Bumps Up Silicon Interposer Costs

Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost.

An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them through an interposer. But silicon interposers are big and expensive. And while alternatives and improvements are under development, there is still much work to be done.

“Interposer fabrication is basically CMOS-type fabrication with different scales (and added through-chip etches),” said Larry Melvin, R&D senior architect at Synopsys.

Today’s interposers often require stitching together of reticle-sized exposures. That approach has been proven to work, but it contributes to high costs more than the die size alone would suggest. “Whenever you start getting into stitching, that’s where a lot of the complexity and the cost adder happens,” said Bassel Haddad, senior vice president and general manager of Skywater Technology.

Others agree. “The usual word that pops up is ‘nightmare,’” said Ken MacWilliams, president of Multibeam.

Efforts are underway to build the process and equipment changes necessary to bring that stitching cost down. Bridges, for example, offer an alternative for very large interposers, which may simplify matters if their assembly yield can be improved.

Fig. 1: Reticle stitching example shows a three-reticle-sized interposer that requires three exposures per layer. The dashed lines highlight stitching boundaries. Source: Bryon Moyer/Semiconductor Engineering

Typical reticle usage
Chip manufacturing costs are heavily dependent on throughput in the fab, which typically is measured by the number of wafers that can be processed per hour. Assuming yield is sufficient, any equipment or process changes that boost throughput will reduce costs.

In steppers, today’s reticles are exposed with 4:1 reduction. That allows masks to be written with larger, more accurate dimensions while still printing features that are one-fourth the size they are on the mask. Smaller chips can have multiple instances in one reticle, boosting throughput.

Historically, each layer required a single exposure, and that’s still the case for small chips. Larger chips mean fewer than four chips per reticle, and in the limit, one reticle holds the contents of just one chip. We tend to say the chip is the size of a reticle, but its actual size will be one quarter the size of the reticle owing to the size reduction.

The delay in extreme ultraviolet (EUV) lithography forced the industry into using double, and in some cases quadruple patterning on 193nm scanners to achieve the desired feature size. Double patterning also requires multiple exposures per layer, but those exposures lie atop each other exactly. Large interposers require multiple exposures, but they’re adjacent to each other rather than stacked vertically. The small amount of overlap necessary between neighboring exposures is what’s called stitching.

Fig. 2: With double-patterning, multiple exposures cover the same area. With stitching, multiple exposures are adjacent with slight overlap. Source: Bryon Moyer/Semiconductor Engineering

Unlike a typical chip that terminates before the edge of a reticle, an interposer may have lines crossing from one exposure to the next. In theory, two exposures could simply abut if lithographers could guarantee perfect alignment. But the real world is not that precise, and so the two exposures must overlap slightly to ensure continuity along the line.

How to best achieve stitching continuity isn’t entirely clear. “Some people think patterns in the stitching regions need larger design rules than the rest of the chip, and others think no designs should connect across stitched regions,” said Synopsys’ Melvin. More experience is necessary before we really know what works best.

Fig. 3: Stitching must create some overlap to accommodate the alignment tolerance and to ensure no feature has continuity breaks. Source: Bryon Moyer/Semiconductor Engineering

Interposers use older processes
Whereas double patterning is employed on the most advanced process nodes, interposers tend to be built on older processes and, significantly, older lithography wavelengths such as 248nm. That reduces the cost below that of 193i technology, or even EUV.

“Interposer dimensions are generally much larger than chip dimensions, so older, less costly technologies such as 248 or 365nm lithography can be used,” noted Melvin.

But it’s also a technology generation that predates through-silicon vias (TSVs). “The TSV requires etching millimeters of substrate in an etch process that is more like a MEMS process (sometimes called the Bosch etch process or Deep RIE) than CMOS,” Melvin observed.

Each reticle scans across an entire wafer, exposing as it goes in a process called step and scan. For multiple patterns, after scanning with the first reticle, the next reticle is aligned, and scanning re-commences on the same wafer. From an exposure-per-wafer standpoint, the cost increase comes from the time needed to swap reticles, since each wafer receives the same number of exposures as it would with a single-reticle die. That’s definitely a cost, but it’s nominal. What’s changed is that the wafer remains in place for all the exposures rather than being swapped out for the next wafer.

“There will be different mask exposures on the same wafer, wafer by wafer, and it’s very time-consuming and lowers the throughput of the scanner,” said Pax Wang, technology development director for advanced packaging at UMC.

From an interposers-per-hour standpoint, however, even though the total number of exposures hasn’t changed, the number of widgets — in this case, interposers — coming out is divided by the number of exposures per widget. That means an abysmal throughput as compared with typical silicon chips.

“The stitching process itself will not impact the yield based on well-designed rules,” said Wang. “However, the stitching will increase the die size and reduce the gross die per wafer and, based on the same defect density, would cause relatively poor yield from die size point of view.”

And that impacts cost. “They are not getting 300 wafers an hour, making three fields of view of interposers,” said Multibeam’s MacWilliams. “That’s part of the reason they’re so expensive.”

Getting worse and getting better
While a 3.3X reticle is TSMC’s current interposer size limit, roadmaps see that going up potentially to as high as 12 reticles. But such an interposer will require an increasingly larger portion of a wafer, potentially leaving more of the wafer periphery unusable.

“Litho is generally the most expensive process on the wafer, taking up 50% of the manufacturing cost in CMOS,” said Synopsys’ Melvin. “Changing litho by adding more reticles will be challenging from a cost-effectiveness point of view. It will not be a 12X increase in cost, though. The cost increase is associated with reticle change times (swap the reticle, align it, then exposure can start) that reduce throughput rates. The larger size also means fewer parts out per interposer wafer. There is also the cost of writing 12 reticles, which can be very expensive.”

Whether that’s economically practical is a huge question, and not everyone thinks silicon interposers will keep getting larger. “I think 3.5 or 4X is going to be a practical limit for how large you can get,” said Mike Kelly, vice president of chiplets/FCBGA integration at Amkor.

An alternative to using wafers to make interposers is panel manufacturing, which is still in development. A rectangular canvas for painting circuits will provide less loss with large rectangular interposers. That could be a way to reduce costs when going to such a large interposer. “Panel technology would make large interposers economically viable,” said UMC’s Wang.

Changing reticle sizes is also theoretically an option, largely driven by the needs of the most advanced nodes, but also applicable to interposers. “There is discussion of a 6-inch x 12-inch reticle,” said Melvin. “This would remove stitching in high-NA EUV. This could extend to a larger reticle format for interposer technology. However, this larger reticle format is controversial because the entire fabrication process is designed to handle a standard reticle size (6-inch x 6-inch), and the cost of the reticle handling retrofit must also be considered. Lots of equipment would have to change to accommodate the new size.”

As mentioned, today’s scanners don’t print a 1:1 image of the mask onto the silicon. Instead, the image size is reduced to 25% of the original reticle size. That creates yet another possible direction. “There is the possibility to change reticle-to-wafer reduction from 0.25X to 0.5X, or even 1X to remove some or all stitching,” said Melvin. “This has cost implications for the interposer mask set and will probably increase mask variability. I do not know if interposer specifications will support the increased mask variability, but my guess is they probably will.”

There may be some help from the scanners themselves, although it’s not clear by how much. ASML has a model with two wafer stages and a single reticle stage. That allows wafers to be loaded or unloaded from one stage while exposure proceeds on the other stage. The intent is to improve throughput, but it doesn’t address the time necessary to swap reticles.

A system with multiple reticle stages could allow loading of all necessary reticles, rotating them into place as necessary. While that saves loading time, alignment is still necessary. One challenge is that the cost savings due to such a change must pay for the cost of developing and acquiring new equipment. Another challenge, perhaps temporary, is that interposers don’t ship in high volumes today, so new equipment may have to await larger volumes to justify the investment.

Will bridges replace large silicon interposers?
Organic interposers are much less expensive than silicon versions, but they can’t provide the line pitch that silicon can. Silicon bridges are a solution to that issue, allowing connections between chiplets that are far narrower than what would be possible on the organic material.

The bridges are small pieces of silicon, giving them high yields and making their cost attractive. They are embedded in cavities in an organic interposer. Ideally, they reduce cost because they provide silicon line/space dimensions without requiring an entire silicon interposer. The challenge is that assembly yields and alignment have been poor, and the process is still being optimized.

“The nice thing about silicon interposers is that the processes and the assembly tech, whether you’re in the foundry or the OSAT space, are really mature,” said Amkor’s Kelly. “The maturity of bridge-based products is much less than silicon interposer-based products.”

Fig. 4: A silicon interposer must be large enough to accommodate all chiplets and components. Bridges allow the use of less expensive organic interposers, with bridges embedded where dense signals are necessary. Source: Bryon Moyer/Semiconductor Engineering

Some believe that improved bridge processes ultimately will replace the largest silicon interposers, if not for cost, then to help with co-planarity. “An organic hybrid with silicon bridges would be the trend to replace pure silicon interposers, because large pure-silicon interposers would suffer warpage issues,” said Wang.

Differences in the coefficient of thermal expansion (CTE) of materials is the primary cause of warpage. “Once you get up into three and a half, four-reticle sizes, you now have a big CTE mismatch between that interposer and the package substrate that it’s going to be soldered to,” Kelly pointed out. “We think the market best-suited for bridges is in large modules. All the high-density work between the die is in the bridge. It’s a high-yielding piece of silicon. And the interconnect density required for the rest of the interposer is quite benign.”

If embedded bridges prove to be a real possibility, it places a question mark on efforts to improve silicon interposer throughput. No one wants to come out with an ideal scanner for large silicon interposers only to find that no one wants them anymore.

That said, signal performance is currently better in silicon interposers than in bridges. Unless that changes, it’s going to relegate bridges to systems demanding lower performance.

No clear solution yet
For the time being, stitching makes large, expensive silicon interposers even more expensive to manufacture. The applications employing such interposers do command high prices, so the existing processes are tolerable.

But for interposers to go more mainstream, the best hope is either that stitching becomes more efficient, raising throughput, or that bridges improve their performance. Without such improvements, advanced packaging will remain limited to high-value systems that can justify the cost.

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