Research Bits: June 8


Multi-tasking transistor Researchers at Pohang University of Science & Technology (POSTECH) developed a zinc oxide (ZnO) and tellurium (Te) heterojunction transistor technology that exhibits negative differential transconductance (NDT), where current decreases over a certain voltage range. By precisely controlling overlap length between the two materials, the team realized double negati... » read more

What’s Next for 2.5D Packaging?


Interposers and bridges, two of the key elements for interconnecting multiple chips and chiplets in an advanced package, are undergoing fundamental changes in how they're built and assembled. Interposers are becoming thicker and more complex, while bridges are being used to reduce the assembled cost. Both efforts are facing new challenges. Interposers are effectively platforms on which mu... » read more

Chip Industry Week in Review


Deals of the week: Arteris announced plans to acquire cybersecurity provider Cycuity. “Expanding our technology portfolio to include Cycuity’s hardware security assurance products will enable our customers to achieve secure on-chip data movement,” said Charlie Janac, chairman and CEO of Arteris. Qualcomm acquired Ventana Micro Systems, a maker of RISC-V data center-class CPU IP. ... » read more

Chip Industry Week in Review


SK hynix is ramping HBM manufacturing capacity to meet explosive demand for AI data centers. The company will launch 16-stack HBM4 next year, and up to 12-stack HBM4E. HBM5 and HBM5E will be introduced between 2029 and 2031, reports Business Korea. China will not have access to NVIDIA’s most advanced chips, President Trump told 60 Minutes. The Dutch economy minister said Nexperia's chip... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs


Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

Chip Industry Week in Review


The U.S. government announced new import tariff actions and deals this week, including: The EU: 15% tariff on most goods including semiconductors. According to the EU's president, the action excludes semiconductor equipment. Copper: 50% tariff on all imports of semi-finished copper products and intensive copper derivative products, effective Aug. 1, but raw input material is excluded. ... » read more

Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Physics Limits Interposer Line Lengths


Electrical interposers provide a convenient surface for mounting multiple chips within a single package, but even though interposer lines theoretically can be routed anywhere, insertion losses limit their practical length. Lines on interposers — and on silicon interposers in particular — can be exceedingly narrow. Having a small cross-section makes such lines resistive, degrading signals... » read more

Chip Industry Week In Review


[Podcast version is here.] TSMC said it will produce 30% of its leading-edge chips in Arizona when all six of its fabs are operational, a total investment of $165 billion, Axios reported. In its latest SEC filing, the foundry said it continues to add capacity in Taiwan, Arizona, Japan, and Germany. The Trump administration launched a Section 232 investigation into semiconductors and relat... » read more

Chip Industry Week In Review


Intel said its new fab in Licking County, Ohio will be delayed due to financial struggles and a need to align chip production with market demand, reported the Columbus Dispatch. Construction is now estimated to be completed in 2030, with operations to start in 2030 or 2031. The company said it already has invested $3.7 billion locally. Apple plans to invest more than $500 billion in the U.S... » read more

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