Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Bosch, Infineon, and NXP were cleared in Germany to each acquire 10% of the European Semiconductor Manufacturing Co. (ESMC), established by TSMC, solidifying the supply chain against future shortages, particularly for automotive chips. “ESMC intends to build and operate another large semiconductor factory in Dresden, in which the three Europ... » read more

Week In Review: Manufacturing, Test


TEL announced plans to build a ¥2.2 billion ($168.2 million) production and logistics center at its Tohoku Office to increase capacity. Construction of the 57,000m² facility, which will be used for manufacturing thermal processing and single-wafer deposition systems, is slated to start in spring 2024, and expected to be completed in fall 2025. Toshiba's board voted in favor of a 2 trillio... » read more

Week In Review: Semiconductor Manufacturing, Test


TSMC is in advanced talks with key suppliers about setting up its first potential European plant in Dresden, Germany, according to Nikkei Asia. The company held a 3nm volume production and capacity expansion ceremony at its Fab 18. TSMC also is building 3nm capacity at its Arizona site, as well as opening a global R&D Center in the Hsinchu Science Park in the second quarter of 2023, to be ... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes


Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Week In Review: Design, Low Power


Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

Week In Review: Design, Low Power


Cadence unveiled a big data analytics infrastructure to unify massive data sets across all Cadence computational software. The Joint Enterprise Data and AI (JedAI) Platform aims to optimize multiple runs of multiple engines across an entire SoC design and verification flow. It combines data from its AI-driven Cerebrus implementation and Optimality system optimization solutions, along with the n... » read more

Week In Review, Design, Low Power


Financial News Cadence announced second quarter revenue of $858 million, an increase of 17.9% compared with the same period a year ago when revenue was $728 million. President and CEO Anirudh Devgan said the company’s results are “emblematic of the megatrends of the long-term strength of semis, systems companies investing more in silicon, and the convergence of system and chip designs.�... » read more

Week in Review: Manufacturing, Test


Fab capacity STMicroelectronics and GlobalFoundries inked a deal to build a new jointly-operated 300mm fab adjacent to ST’s existing 300mm facility in Crolles, France. This facility is targeted to ramp at full capacity by 2026, with up to 620,000 300mm wafer per year production at full build-out (~42% ST and ~58% GF). The new facility will support several technologies, with a special focus... » read more

Auto Chipmakers Dig Down To 10ppb


How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them. Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, ... » read more

Fabs Drive Deeper Into Machine Learning


Advanced machine learning is beginning to make inroads into yield enhancement methodology as fabs and equipment makers seek to identify defectivity patterns in wafer images with greater accuracy and speed. Each month a wafer fabrication factory produces tens of millions of wafer-level images from inspection, metrology, and test. Engineers must analyze that data to improve yield and to reject... » read more

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