Week In Review: Manufacturing, Test

Toshiba favors takeover bid; ASIC publishes National Advanced Packaging Manufacturing Program whitepaper; SEMI’s World Fab Forecast; Nova opens new facility; Samsung’s first UWB chipset, NVIDIA tweaks chip for China and announces Quantum processor.


TEL announced plans to build a ¥2.2 billion ($168.2 million) production and logistics center at its Tohoku Office to increase capacity. Construction of the 57,000m² facility, which will be used for manufacturing thermal processing and single-wafer deposition systems, is slated to start in spring 2024, and expected to be completed in fall 2025.

Toshiba‘s board voted in favor of a 2 trillion yen ($15.3 billion) buyout led by Japan Industrial Partners, an industrial consortia that could then be on a path to go private after it is sold, according to Nikkei Asia.

The American Semiconductor Innovation Coalition (ASIC) unveiled a white paper that details how NIST and the U.S. Department of Commerce could establish the National Advanced Packaging Manufacturing Program (NAPMP) as a hub for chip manufacturing. Despite allocating $2.5B to chips in the first year, NIST’s direction for the NAPMP has been sparse. The white paper proposes a structure for the NAPMP focused on “Coalitions of Excellence,” outlines the relationship between a NAPMP and NSTC, and discusses how to involve multiple private and public sector organizations.

Nova opened a new facility with the goal of  doubling production capacity in the next five years. “The new clean room in Israel can support higher yield for our established products but also accommodate high-volume manufacturing of our new products,” said Eitan Oppenhaim, Nova’s President and CEO. “Built with ESG principles in mind, the new facility meets high industry standards for a safe and smart work environment to enable cutting-edge production.

MITRE Engenuity announced the formation of an advisory council to boost the impact and expand the focus of the Center for Threat-Informed Defense. The goal is to expand the center’s R&D focus and its industry partnerships, “truly changing the game on the adversary.”

NVIDIA tweaked its flagship H100 chip for export to China, according to Reuters. (In November, NVIDIA reduced some capabilities of its A100 chip to create a new export-legal A800 chip.) The new chip, called the H800, is being used by the cloud computing units of Chinese technology firms such as Alibaba Group Holding, Baidu and Tencent Holdings Ltd.

In addition, NVIDIA announced the NVIDIA DGX Quantum, built with Quantum Machines, a new system that provides a novel architecture for researchers working in high-performance and low-latency quantum-classical computing. The world’s first GPU-accelerated quantum computing system, the DGX Quantum features an NVIDIA Grace Hopper system connected by PCIe to Quantum Machines OPX+, enabling sub-microsecond latency between GPUs and quantum processing units (QPUs).

Synopsys, ASML, and TSMC are integrating NVIDIA’s cuLitho software library for computational lithography into their respective processes and systems. Synopsys will run its optical proximity correction (OPC) software on the cuLitho software library. “Running on GPUs, cuLitho delivers a performance leap of up to 40X beyond current lithography — the process of creating patterns on a silicon wafer — accelerating the massive computational workloads that currently consume tens of billions of CPU hours every year,” NVIDIA said.

The Wall Street Journal examined workforce challenges associated with Micron moving from Boise to Syracuse, including whether the area’s universities can provide workers and training.

Samsung announced its first ultra-wideband (UWB) chipset, the Exynos Connect U100. With single-digit centimeter accuracy, the new UWB solution is optimized for use in mobile, automotive and Internet of Things (IoT) devices, offering precise distance and location information. The company also unveiled Exynos Connect, a new brand that consolidates its short-range wireless communication solutions, such as UWB, Bluetooth, and Wi-Fi.

SkyWater Technology announced it has established a new cryogenic lab to characterize random telegraph signal (RTS) noise for read-out integrated circuits (ROICs). Mitigating RTS noise is crucial to improving the image quality and performance for ROIC customers in various applications such as night vision, military surveillance, as well as industrial and automotive thermal imaging.

Stuart Pann is the new general manager of Intel Foundry Services. Pann, an Intel and HP veteran, will report directly to CEO Pat Gelsinger.

Renesas and Flexciton teamed to conduct a successful trial of Flexciton’s next-gen scheduling software, which adds more intelligence than current heuristic approaches. Timelink constraints define the maximum allowed time between steps in the production of a wafer.

Lithoptek announced the release of the CD Optimizer (CDOP) semiconductor processing tool. The CD Optimizer has been demonstrated to reduce systematic variations of CD (improving CD uniformity, or CDU) on silicon wafers by as much as a factor of four.

QP Technologies has extended its broad plastic package assembly portfolio with two new offerings — a 64-pin thin quad flat pack (TQFP) and a 52-pin metric quad flat pack (MQFP) plastic encapsulated package. QP says the options are ideal for military-aerospace (mil-aero), automotive, industrial and other applications requiring cost-sensitive, robust device packaging that provides high thermal and electrical performance.

Market Research

Global fab equipment spending for front-end facilities is expected to decrease 22% year-over-year (YoY) to US$76 billion in 2023 from its record high of US$98 billion in 2022, before rising 21% YoY to US$92 billion in 2024 to reclaim lost ground, SEMI announced in its latest quarterly World Fab Forecast report. The decline will be the result of weak chip demand and higher inventory of consumer and mobile devices. Next year’s fab equipment spending recovery will be driven in part by the end of the semiconductor inventory correction in 2023 and strong demand in high-performance computing (HPC) and automotive segments.

Fig.1: Front end fab equipment spending. Source: SEMI


The Semiconductor Industry Association (SIA) commended the introduction in Congress of bipartisan legislation to restore full tax deductibility of R&D investments. The legislation, the American Innovation and Jobs Act, was introduced in the Senate by Maggie Hassan (D-N.H.) and Todd Young (R-Ind.), along with 10 other co-sponsors. “Restoring the decades-long policy of allowing the immediate, full deduction of R&D investments would help make the U.S. a more competitive place for R&D and innovation, boost economic growth and job creation, and attract and retain talented workers. We look forward to working with leaders in Congress to get this bipartisan, commonsense initiative across the finish line in short order,” said SIA President and CEO John Neuffer.

Researchers from the University of Geneva (UNIGE), the Geneva University Hospitals (HUG), and the National University of Singapore (NUS) have developed a novel method for evaluating the interpretability of AI, shedding light on ‘‘black box’’ AI algorithms. The research carries particular relevance in the context of the forthcoming European Union Artificial Intelligence Act which aims to regulate the development and use of AI within the EU.

A new technology to combine optics and micro-electro mechanical systems (MEMS) in a chip has been developed at Australia’s University of Sydney. It could pave the way for the creation of devices like micro-3D cameras and gas sensors for precision air quality measurement, including their use in mobile phones.

Further reading

Read about the challenges of developing metrology solutions for 2nm processes, silicon photonics standards, and other issues in our recent Test, Measurement & Analytics Newsletter:

Check out our Fab Process Forecast and other hot topics in our Manufacturing, Packaging & Materials newsletter:

Upcoming events:

  • International Reliability Physics Symposium (IRPS), Mar. 26 – 30 (Monterey, CA)
  • International Symposium on Physical Design (ISPD), Mar. 26 – 29 (online)
  • TinyML Summit, Mar. 27 – 29 (San Francisco, CA)
  • Design, Automation and Test in Europe Conference, Apr. 17 – 19 (Antwerp, Belgium)
  • Critical Manufacturing/Hannover Messe, Apr. 17 – 21 (Hannover, Germany)
  • Advanced Semiconductor Manufacturing Conference (ASMC), May 1 – 4 (Saratoga Springs, NY)

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