Every Atom Now Counts In Advanced Chip Manufacturing

Artificial-intelligence workloads are pushing semiconductor design to a point where traditional scaling strategies are running out of room. Performance improvements that once came from shrinking transistors now depend increasingly on how devices are stacked, interconnected, and isolated. Transistor scaling still matters, but advanced device architectures no longer can accommodate the power density and bandwidth demands of multi-kilowatt AI systems.

The result is a deeper dependence on materials that must maintain electrical, mechanical, and chemical stability under increasingly extreme conditions. Thin-film dielectrics, conformal metal barriers, and atomic-scale interfaces now play an active role in determining power efficiency, signal integrity, and long-term reliability. As AI accelerators expand in size and complexity, these films are forced to perform across more aggressive aspect ratios, tighter pitches, higher temperatures, and more demanding integration steps.

“Dimensional shrinking in 2D is getting closer to its limits,” said Hichem M’Saad, CEO of ASM International. “So devices are moving into 3D. Once you go that direction, you get better performance by having new materials.”

The result is an architectural shift that elevates materials engineering to the center of semiconductor progress. Gate dielectrics, etch-stop layers, liners, nucleation films, and encapsulation materials are no longer treated as passive unit processes. They influence device behavior, interconnect performance, and overall system characteristics. Achieving high performance increasingly requires deposition techniques capable of controlling matter one atomic layer at a time.

Atomic-layer deposition
Atomic-layer deposition (ALD) has become indispensable for managing these challenges, especially on the front end. ALD is not new, but its importance has surged as device dimensions approach scales where the number of atoms in a film becomes a limiting factor. High-k gate dielectrics, spacers, liners, nucleation layers, and work-function materials all benefit from ALD’s angstrom-level thickness control. BEOL interconnects also use ALD for diffusion barriers, caps, and etch-stop films, where aspect ratios exceed the reach of traditional PVD or PECVD.

Unlike line-of-sight deposition, ALD’s sequential surface reactions let each atomic layer form uniformly, even in deep or narrow structures. This precision opens pathways to entirely new compounds and nanolaminates tailored for specific electrical, mechanical, or thermal properties. In practice, it enables foundries to create dielectric and barrier films that would be impossible to fabricate by any other means.

“ALD is becoming necessary, especially for gate-all-around,” said Victor Moroz, fellow at Synopsys. “You build the structure one atom at a time and look at the surface reactions and how the next atom attaches. You try to make the chemistry such that the kink sites are more attractive, so you grow one monolayer at a time.”

Uniformity is more than a convenience for these structures. It’s foundational. Even a small variation in ALD thickness can shift electrostatic control or introduce leakage pathways that accumulate across billions of transistors.

“These structures are getting really complex,” said Joseph Ervin, managing director of Semiverse Solutions at Lam Research. “The 3D geometries make it very challenging to make sure films are conformal. You can certainly go build and test it, but it takes a lot of iterations to get through. We use simulation to explore that space, such as how deposition occurs across the structure and how things diffuse on the surfaces to shorten the design cycle and get to a solution faster.”

Fig. 1: Simulation of atomic layer deposition. Source: Lam Research

“At the transistor level, conformality is essential,” added Moroz. “Between the adjacent channels, there’s about 10 or 11 nanometers of space, and you have to deposit the dielectric conformally from both sides. That takes about 2.5 nanometers on each side, so you only have 5 or 6 nanometers left for metal. You have to deposit this dielectric first and then the metal in that tiny space.”

To achieve that level of precision, other deposition techniques are evolving as complementary solutions. “We can call it sputter epitaxial growth,” said Michael Schneider, vice president of semiconductors and precision optics for Von Ardenne. “During each revolution of the disk, you get a thickness increase of roughly one monolayer, or about 0.1 nanometers. This provides extremely precise control over the film’s thickness.”

Sputter epitaxy doesn’t replace ALD for conformal structures, but it does provide an alternative for planar or symmetric layers that demand uniform stress and thickness control across large areas. It reflects how multiple thin-film approaches are now being tuned together to achieve atomic-level uniformity across different geometries.

ALD surface chemistry
ALD’s defining characteristic is its self-limiting surface chemistry. Films grow one monolayer at a time through alternating precursor pulses. Each pulse reacts with surface termination sites until they are fully consumed, allowing for extremely uniform deposition even in deep or narrow structures.

“Moore’s Law right now is being driven more and more by new materials,” said M’Saad. “The best technique to deposit new material is ALD, because its self-limiting nature makes it possible to innovate and create new materials.”

Fig. 2: ALD process flow. Source: ASM

This mechanism is ideal for aggressive geometries, but it introduces unique engineering challenges. The chemistry must favor complete surface coverage without allowing uncontrolled nucleation. Minor contamination or non-ideal reaction kinetics can cause film discontinuities that multiply with each cycle.

“At these thicknesses, crystallinity becomes a liability,” said Moroz. “Grain boundaries act as diffusion paths and electrical-leakage channels. That’s why most high-k dielectrics are kept amorphous. Once you have crystalline regions, they form polycrystalline boundaries. Those become troublemakers because contamination collects there, creating leakage and threshold-voltage shifts.”

For this reason, many advanced dielectrics are intentionally engineered to remain amorphous. As the material landscape expands, atomic-scale modeling is becoming essential for predicting how surface reactions and local bonding environments affect film growth.

“The next step is coupling these atomistic models to the larger system-level simulations,” said Marc Swinnen, director of product marketing at Synopsys. “When you can link deposition dynamics directly to electrical and thermal simulations, you close the loop between materials, process, and performance.”

“You can only sample so much experimentally,” added Lam’s Ervin. “Virtual simulations let you explore a much bigger design space, and machine learning makes that exploration much more efficient,” said Lam’s Ervin. “You get more predictions and can drive to a solution faster.”

Growing materials complexity
As AI accelerators grow more complex and device architectures push into nanosheet and forksheet regimes, the materials used in FEOL and BEOL stacks have multiplied. High-k oxides, metal gates, multilayer nitride spacers, cap layers, etch stops, low-k ILDs, ultra-low-k dielectrics, and exotic metal barriers all require different plasma conditions and precursor chemistries.

“When ASM started in Phoenix in 1976, we only had a handful of elements in the semiconductor space and zero deposited by ALD,” said M’Saad. “Today, about 75% 5o 80% of all the elements in the periodic table are used in the semiconductor space and deposited by ALD. As we understand ALD better and as more R&D dollars go into it, we’re developing new films and hardware that give even better control than ever before.”

This wider palette enables more options but also increases integration risk. Interfaces between layers can undergo intermixing, diffusion, or dipole formation that alters electrical behavior. Some layers exist only transiently during processing and then disappear through etching or mixing. Those challenges have made early collaboration and design-stage coordination essential.

“The key is working together with stakeholders in the early stages of selecting materials to include desired chemical and physical properties,” said Amit Kumar, senior applications engineer at Brewer Science. “Modifying a material later, when most of the stack properties are set, is more challenging than building a material stack system.”

In practice, that means materials suppliers must align closely with both equipment makers and design teams to anticipate how each film will behave through successive process steps. Integration issues that once could be patched later in development now have to be modeled, simulated, or compensated for at the concept stage. Toolmakers are beginning to share more process data upstream, while materials companies are adjusting chemistries for compatibility across etch, deposition, and packaging environments.

“Working with the supply chain to collaboratively address the material requirements and design the material functionality around the application is beneficial to address the complexity,” added Kumar. “Integrating the design tools as guidelines for developing material solutions is another approach for enhanced feasibility.”

Balancing stress and conformality
The shift toward thinner, more complex stacks adds new concerns about mechanical stability and film stress. Even relatively low levels of stress can distort structures, shift critical dimensions, or affect downstream bonding. As dielectrics grow thinner and more chemically diverse, internal stress becomes inseparable from film composition and deposition method.

“When depositing material, you inherently introduce film stress, which can cause substrate warpage,” said Schneider. “That can be minimized by adjusting specific process parameters or by using different power configurations for the sputtering process. Another strategy is to compensate for the stress by coating the backside of the substrate simultaneously, creating geometric balance and reducing deformation.”

Sputtering’s directional energy transfer gives engineers the ability to manipulate intrinsic stress through plasma power, gas pressure, and substrate biasing. By controlling these parameters, thin films can be tuned for compressive or tensile characteristics, which are critical for preventing bowing in large wafers or multilayer stacks. In applications like redistribution layers or wafer-level caps, how stress is balanced can directly impact yield and downstream alignment accuracy.

Film-stress compensation strategies like these are becoming a vital part of process integration. Some ALD and CVD systems now incorporate dynamic plasma control or dual-sided processing to balance mechanical loads during long deposition cycles. Engineers also use thermal ramping and staged precursor dosing to modulate film densification rates, preventing residual stress from building at layer interfaces.

“We are simulating how these films build up stress and what the impact is at the feature level,” said Ervin. “When you’re trying to build features down to the nearest angstrom, any deviation of even a nanometer is important. So we’re looking at these effects with a level of accuracy that lets us understand where stress may cause problems.”

The tradeoff between stress and conformality is becoming one of the defining challenges of advanced packaging and transistor fabrication. ALD provides unmatched uniformity, but its slower growth rate and high film density can create brittle layers when stacked without proper stress relief. PECVD and sputtering, by contrast, offer higher throughput and more tunable film flexibility, but they struggle to maintain uniform composition in extreme aspect ratios.

Process engineers increasingly combine these approaches within hybrid dielectric stacks, which combine inorganic and organic dielectrics. A low-stress sputtered or PECVD layer may provide mechanical buffering beneath a dense ALD barrier or high-k dielectric, while backside coatings or liner films distribute stress symmetrically. These strategies reflect a broader realization — film reliability now depends as much on mechanical balance as on electrical performance.

“Beyond developing the tool itself, much of the challenge lies in fine-tuning the process and accurately measuring what happens during deposition,” added Daniel Radach, sales director for PV technology at Von Ardenne. “We monitor everything in-situ to determine when to stop a deposition and when to switch materials. That level of precision becomes increasingly important as feature sizes shrink.”

As layer counts increase and tolerance windows narrow, process engineers are leaning more heavily on real-time monitoring, closed-loop control, and digital-twin simulation to achieve the required atomic precision across larger wafer surfaces.

Precision and process control
As deposition processes approach atomic limits, precision depends on how accurately each reaction can be measured, repeated, and corrected. Self-limiting reactions make ALD inherently stable, but as cycle counts climb into the thousands, even minute changes in temperature, pressure, or precursor flow can create measurable non-uniformity across a wafer.

“Foundries strictly enforce conformality because that’s easy to measure,” said Moroz. “Composition uniformity is more difficult to measure and enforce. You cannot guarantee what you cannot measure, so what is easier to measure gets perfected faster.”

The industry is responding by embedding sensors deeper into the process. Advanced reactors now monitor multiple temperature points across the wafer, plasma species concentration, gas flow rates, and chamber pressure gradients in real-time. Those signals increasingly are fed into machine-learning control systems that can detect subtle pattern drift long before it translates into yield loss.

“Tooling changes over time have a physical cause,” said Ervin. “In the digital-twinning work, we try to capture the effects that are actually happening in real-time. We get feedback from the equipment and from the experiments we run, and we bring that information back into the simulation space.”

Simulation reinforces those controls. Using multi-scale models, process engineers can link atomic-level surface reactions to macroscale film growth rates and predict how chamber dynamics will alter deposition at the edge versus the center of the wafer.

“The industry is using atomistic modeling to build structures one atom at a time and evaluate how each reaction site behaves,” said Moroz. “We can predict where conformality might break down or where imperfections could occur for a given chemistry.”

At higher levels of abstraction, these insights are being integrated directly into electronic design automation tools. Variations in dielectric thickness, interface charge density, or stoichiometry can be represented statistically in process design kits (PDKs), allowing circuit designers to assess performance sensitivity before tapeout.

This type of variation modeling feeds directly into the digital-twin approach. “Digital twins allow you to evaluate how small chemical or mechanical variations translate into measurable parametric shifts. That’s critical when you’re designing around nanometer-scale tolerances,” said Swinnen.

Interfaces, reliability, and stack integration
As the dielectric stack becomes thinner and more complex, it’s the interfaces, rather than the bulk films, that increasingly govern reliability. Each boundary introduces potential mismatches in lattice spacing, charge distribution, and thermal expansion, which can lead to delamination, corrosion, or time-dependent dielectric breakdown.

“With ALD, the film is very thin, so you need to control the interface,” said M’Saad. “When you deposit an ALD film as thin as five angstroms, that interface becomes a big deal. We prepare and clean the surface before deposition to ensure good adhesion and minimize defects.”

ALD’s layer-by-layer precision allows engineers to design these interfaces in great detail. Dipole layers — often lanthanum or aluminum oxide — can fine-tune band alignment between the dielectric and the channel material, adjusting transistor threshold voltage without changing geometry.

“The fact that you can control every monolayer you deposit means you can actually engineer your own surface,” added M’Saad.

Surface preparation remains one of the most delicate steps. Native oxides, carbon residues, or trace halogens can disrupt ALD’s self-limiting reactions, producing pinholes or incomplete coverage. Toolmakers are responding with plasma-based cleaning and vacuum transfer modules that preserve surface termination between steps.

“When you thin out a material, you lose all the bulk properties of that material,” said Douglas Guerrero, senior technologist at Brewer Science. “We’re beginning to look at films just a few molecules thick, which makes maintaining performance much more challenging.”

Those molecular-thick layers can behave more like membranes than solids. Their thermal expansion, mechanical modulus, and chemical reactivity differ radically from bulk versions of the same material. As a result, downstream processes like etch, planarization, and packaging must now be co-engineered with the film stack rather than treated as post-deposition steps.

Because each layer adds its own mechanical and chemical interactions, long-term reliability now depends on how the entire stack evolves through thermal and chemical cycling. Low-k polymers, dense ALD barriers, and CVD oxides expand at different rates under heating, and repeated stress can cause delamination unless adhesion and modulus are carefully balanced.

Hybrid dielectric strategies
No single deposition technology can meet all requirements for today’s multi-function stacks. The trend across logic, memory, and advanced packaging is toward hybrid dielectric integration, combining ALD for conformal seed layers with CVD or PECVD for thickness and mechanical reinforcement.

The complementary nature of ALD and other thin-film methods is becoming more deliberate. “For conformal coating in vias, it’s a bit tricky with magnetron sputtering because it’s a more directed process,” said Von Ardenne’s Schneider. “I don’t think we can fully replace ALD in cases where extremely thin and highly conformal coatings are required, but we can complement it.”

Von Ardenne’s sputter epitaxial growth approach uses precise rotational control to achieve near-monolayer uniformity. These sputter systems are becoming more relevant as the industry seeks throughput without sacrificing precision. For planar layers, such as diffusion barriers or conductive caps, they can deliver sub-nanometer accuracy at speeds that ALD cannot match. Meanwhile, hybrid stacks combine ALD’s conformality with sputtering’s dense microstructure and tunable mechanical stress.

“When depositing material, you inherently introduce film stress, which can cause substrate warpage,” Schneider added. “That can be minimized by adjusting specific process parameters or by using different power configurations for the sputtering process. Another strategy is to compensate for the stress by coating the backside of the substrate simultaneously, creating geometric balance and reducing deformation.”

Hybrid dielectric stacks are becoming increasingly customized. ALD may provide the nucleation or barrier layer, followed by a thicker CVD or PECVD film for mechanical strength, then capped with a spin-on or plasma-cured polymer for planarity and ultra-low permittivity.

In heterogeneous integration, these combinations extend into redistribution layers, interposers, and package-level passivation, creating a single continuum of dielectric engineering from the front end through assembly.

Conclusion
As semiconductor manufacturing pushes into new physical and architectural regimes, thin-film dielectrics have become central to both performance and reliability. Device behavior now depends as much on the atomic-level precision of the dielectric stack as on the geometry of the transistor itself. The continued rise of heterogeneous integration, dense interconnect meshes, and multi-kilowatt AI accelerators has placed unprecedented demands on film uniformity, conformality, and interface stability.

Atomic layer deposition sits at the center of this shift. Its self-limiting reactions, surface-selective chemistry, and ability to coat extreme aspect ratios make it indispensable for gate-all-around transistors, metal gate stacks, inner spacers, and advanced barrier layers. But the same qualities that make ALD powerful also expose its sensitivity to contamination, precursor purity, reactor stability, and chamber material integrity. As films thin toward their physical limits, every atom begins to matter.

PECVD, CVD, and sputtering processes still play essential roles, particularly in low-k and ultra-low-k integration, where mechanical stability and throughput remain critical. But these methods increasingly rely on ALD layers for nucleation, densification, or protection, reflecting a broader trend toward hybrid dielectric strategies that combine multiple techniques for a single functional purpose.

The next phase of scaling will be defined by deliberate engineering of the materials that surround them, not just by smaller features. ALD and advanced dielectric processes provide the precision needed for this transition, but they also require unprecedented coordination across the supply chain. As AI workloads grow and architectures diversify, dielectric films will continue to determine the speed, stability, and efficiency of the systems built upon them.

Semiconductor progress often is described as a story of shrinking transistors. Increasingly, it is becoming a story of the materials between them.