tag: 3D integration

Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Grenoble INP - UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, a... » read more

Wafer-on-Wafer Hybrid Bonding: Reticle Placements To Achieve Efficient NW Topologies (ETH Zurich)
By Technical Paper Link - 09 Mar, 2026 - Comments: 0

Researchers from ETH Zurich published the new technical paper "Network Design for Wafer-Scale Systems with Wafer-on-Wafer Hybrid Bonding." Abstract "Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by p... » read more

Making Hybrid Bonding Better
By Laura Peters - 02 Mar, 2026 - Comments: 0

Key Takeaways Fab processes are optimizing for cleanliness, planarity, and high bond quality. Nanotwinned copper and SiCN PVD enable lower anneal and deposition temperatures for HBM. A thin, protective layer helps preserve the Cu/dielectric during aggressive processes. The future of semiconductor manufacturing is no longer dependent just on shrinking features. Instead, chipm... » read more

Why Indium Oxide Chips Are Getting So Much Attention
By Katherine Derbyshire - 19 Feb, 2026 - Comments: 0

Key Takeaways Their low leakage is of interest for memory applications, particularly capacitor-less gain cell designs; They can be deposited over large areas using low-temperature processes, a very desirable characteristic for BEOL integration, and The variety of compositions available gives designers many options to achieve the specific properties they need. Indium tin oxide (ITO), ... » read more

Every Atom Now Counts In Advanced Chip Manufacturing
By Gregory Haley - 22 Jan, 2026 - Comments: 0

Artificial-intelligence workloads are pushing semiconductor design to a point where traditional scaling strategies are running out of room. Performance improvements that once came from shrinking transistors now depend increasingly on how devices are stacked, interconnected, and isolated. Transistor scaling still matters, but advanced device architectures no longer can accommodate the power dens... » read more

The Thermal Trap: How Dielectrics Limit Device Performance
By Gregory Haley - 20 Nov, 2025 - Comments: 1

The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

Edge AI Safety: Agentic AI Architecture That Leverages 3D To Integrate A Dedicated Safety Layer (Princeton, HKUST, NC State Univ.)
By Technical Paper Link - 17 Nov, 2025 - Comments: 0

A new technical paper titled "3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence" was published by researchers at Princeton University, Hong Kong University of Science and Technology, and North Carolina State University. Abstract "AI systems have found a wide range of real-world applications in recent years. The adoption of edge artificial intelligence, ... » read more

A Fundamental Rethinking Of Memory Hierarchy Design (Stanford University)
By Technical Paper Link - 05 Sep, 2025 - Comments: 0

A new technical paper titled "The Future of Memory: Limits and Opportunities" was published by researchers at Stanford University and an independent researcher. Abstract "Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large ... » read more

Transformation Of 2D-ICs Into 3D-ICs Using Shuttle Chips From Multi-Project Wafers (Tohoku University)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding" was published by researchers at Tohoku University. Abstract "Three-dimensional integrated circuit (3D-IC) technology, often referred to as through-silicon via (TSV) formation technology, has been steadily maturing and is increasingly used in advanced semic... » read more

3D Photonic Integration For Ultra-Low-Energy, High-Bandwidth Interchip Data Links (Columbia et al.)
By Linda Christensen - 23 Mar, 2025 - Comments: 0

A new technical paper titled "Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links" was published by researchers at Columbia University, Cornell University, Air Force Research Laboratory Information Directorate and Dartmouth College. Abstract "Artificial intelligence (AI) hardware is positioned to unlock revolutionary computational abilities by ... » read more

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