Advancing 3D Integration

A look at some of the many ways to stack chips.


Jerry Tzou’s recent presentation on 3D Fabric Technology was all about More than Moore. TSMC has other specialized technologies such as RF and eNVM, but this is a general foundational technology for hyperscale data centers, mobile, and AI.

Jerry started with the motivation for using chiplets and heterogeneous chip integration. You can see in the diagram below on the left where die from node N can be mixed with die from earlier (cheaper) nodes. This can result in better cost and time to market.

TSMC has three primary 3D integration technologies that it brands together under the name 3DFabric. These are two back-end technologies, CoWoS (chip-on-wafer-on-substrate), InFO (integrated fan-out), and SoIC (system-on-integrated-chips). These all have different costs, and the technologies have different maturities.

CoWoS is the most mature, having been in use for a decade. It is a chip-last technology and is best suited to very high performance designs, especially if they are running into reticle size limitations. InFO is a chip-first technology, suitable for smaller, more highly integrated designs. The newest technology, announced last year, is SoIC which is a 3D stacking technology with two sub-genres: chip-on-wafer (CoW) where multiple chips of different sizes can be assembled, and wafer-on-wafer (WoW) where two wafers are joined face to face. There are two disadvantages with WoW: the die need to be the same size so that they line up when the wafers are fused, and the fact that the process does not involve known-good-die (KGD) and so any die that doesn’t yield is going to be taking its opposite number good die down with it.


There is a new InFO_B (bottom-only) to go with the existing InFO_PoP which allows LPDDR DRAM package stacking at the contract manager (as opposed to TSMC). This is sometimes required for a customer whose supply chain model requires it. The new InFO_B enhances performance with deep-trench-capacitor (DTC) and lower parasitics. It can house larger chips with tighter pitches. It is optimized for mobile chips in the smallest possible form factor.

InFO_oS (for “on substrate) is targeted to HPC applications. It can currently go up to twice the reticle size, with plans to go up to 2.5 times the reticle size, along with corresponding higher capacity and speed. This will be qualified later this year and TSMC expects to have more than ten products using it from more than four customers (by end of 2021).

There is another larger InFO_oS with a huge 110mm by 110mm substrate, 5 RDL layers, and a C4 pitch of 130um. It has a fairly standard chiplet scheme with two logic die and eight I/O die around it. It has passed its early assessment reliability. They expect this configuration to cover a wide range of floorplans and package sizes.


CoWoS is aimed primarily at applications in HPC that need to integrate advanced logic and HBM. TSMC expects over 100 product tapeouts from over 15 customers by the end of 2021. Thicker interconnect metal and eDTC enhances PDN performance. The target is to qualify 3-reticle size by the end of this year.

To reduce CoWoS time-to-market, TSMC is introducing CoWoS-S STAR (for STandard ARchitecture). It has had a 100% success rate for STAR adopters in 2020. This year it will extend STAR to larger reticles and more floorplans. The rate of adoption of STAR will increase by 4X in 2021. There are plans to extend this standard approach to InFO_oS, too.

Since HPC designs may dissipate hundreds of watts (or even over a thousand) good thermal solutions are required, with a variety of Thermal Interface Materials (TIMs): gel, film, or metal can lower the package thermal resistivity by as much as 85% when used with a lidded package design.


As I mentioned briefly above, SoIC consists of two basic technologies with different tradeoffs.

For WoW, qualification is at the end of this year. For CoW, N7-on-N7 should be qualified in Q4 with N5-onN5 following in 3Q 2022. The SoIC roadmap is in the diagram below:


Jerry wrapped up with a map showing where the advanced packaging and test manufacturing sites are located. The latest, AP6, is under construction and expected to start operation in late 2022.

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