A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Abstract "With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and sol... » read more

Advancing 3D Integration

Jerry Tzou's recent presentation on 3D Fabric Technology was all about More than Moore. TSMC has other specialized technologies such as RF and eNVM, but this is a general foundational technology for hyperscale data centers, mobile, and AI. Jerry started with the motivation for using chiplets and heterogeneous chip integration. You can see in the diagram below on the left where die from node... » read more

New Ways To Optimize Machine Learning

As more designers employ machine learning (ML) in their systems, they’re moving from simply getting the application to work to optimizing the power and performance of their implementations. Some techniques are available today. Others will take time to percolate through the design flow and tools before they become readily available to mainstream designers. Any new technology follows a basic... » read more

Debate Over Health Of Moore’s Law Continues

Semicon West 2019 was kicked off by the ‘AI Design Forum’ and featured a panel of CEOs that debated if Moore’s Law was still making power, performance and area optimization possible in the same way as it had been. Synopsys chairman and co-CEO Aart de Geus asserted that Moore’s Law is completely alive. “The discussion of Moore's Laws invariably goes back to the ‘65 document, and t... » read more

Power Becomes Bigger Issue In Stacked Die

By Ed Sperling Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die. While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—t... » read more

Analog Hits The Power Wall

By Ed Sperling Analog design teams are starting to encounter the same physical issues that digital design engineers began wrestling with several nodes ago—only the problems are more complicated and even more difficult to solve. At advanced nodes digital circuitry is susceptible to an array of physical effects ranging from heat, electromigration, electromagnetic interference and electrosta... » read more

Preparing For 3DX

By Aveek Sarkar Undoubtedly we live in the age of mobility—smartphones, tablets, and ultra-books have transformed the way we work, live, and communicate. The worldwide smartphone market’s forecasted 24% CAGR, between 2010 and 2015 provides unique opportunities1. In emerging economies, more than 1 billion consumers are ready for the next new mobile platform2. Success in this market demands ... » read more

Getting In the Ballpark

I admit it; I still have DAC on the brain. Even though attendance may not have been what the exhibitors would have liked to see, the conference is always a fantastic place to discuss ideas and pick up on trends. One topic I discussed with a number of folks are the challenges associated with design today, from the power-performance balance, 3D stacking to new process nodes and complexity, to nam... » read more

All Indicators Point North

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

Fabless-Foundry Model Under Stress

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

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