EDA Gears Up For 3D


Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

What Next For OSATs


Semiconductor Engineering sat down to discuss IC-packaging and business trends with Tien Wu, chief operating officer at Taiwan’s Advanced Semiconductor Engineering ([getentity id="22930" comment="ASE"]), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor. What follows are excerpts of that conversation. SE: What’s the outlook for the IC industry in 2017? Wu:... » read more

Is The 2.5D Supply Chain Ready?


A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

Foundry Landscape Changes In 3D


By Mark LaPedus Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing. One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, T... » read more