Runaway complexity is making it more difficult and critical to deal with signal integrity in a system context.
ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power.
While terms often are used interchangeably, they are very different technologies with different challenges.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Key pivot and innovation points in semiconductor manufacturing.
Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.
Thinner photoresist layers, line roughness, and stochastic defects add new problems for the angstrom generation of chips.
Less precision equals lower power, but standards are required to make this work.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
127 startups raise $2.6B; data center connectivity, quantum computing, and batteries draw big funding.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Thermal mismatch in heterogeneous designs, different use cases, can impact everything from accelerated aging to warpage and system failures.
Technical and business challenges persist, but momentum is building.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
New memory standard adds significant benefits, but it’s still expensive and complicated to use. That could change.
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