Ethernet’s Next Life


An ever-growing engagement with the Internet — where most of humanity and the ‘things’ we use are almost constantly connected and constantly storing, processing and retrieving data over a network — is increasing pressure to develop new standards, and much more quickly. Witness the timeline of Ethernet, and its humble beginnings as a standard protocol for moving data at 2.5 megabits p... » read more

Efficient Verification Of Mixed-Signal SerDes IP Using UVM


Interface IP is an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal v... » read more

SerDes Signal Integrity Challenges At 28Gbps And Beyond


After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization... » read more

From SerDes Chiplets To Die-To-Die Interfaces


The demand for ever faster high-speed interfaces has never been quite so pronounced. In our increasingly connected world, petabytes of data are continuously generated by a wide range of devices, systems and IoT endpoints such as vehicles, wearables, smartphones and even appliances. The resulting digital tsunami has prompted industry heavyweights like Google, Microsoft, Facebook and Amazon to co... » read more

The SerDes – Terabit Ethernet Connection


400 Gigabit Ethernet (400GbE) and 200 Gigabit Ethernet (200GbE) are currently slated for official release by the IEEE P802.3cd Task Force in December 2017. Although there is not yet an official IEEE roadmap detailing what lies beyond 400GbE, doubling to 800GbE will likely become a reality when single-lane 112Gbps links hits the market. This technology will allow for larger lane bundles, providi... » read more

Understanding SerDes Signal Integrity Challenges


Signal integrity (SI) can perhaps best be defined as a set of measures of the quality of electrical signals, which are subject to the effects of noise, distortion and loss. Additional signal integrity issues include jitter, ringing, crosstalk, ground bounce and power supply noise. There are multiple factors that can negatively influence signal integrity, thereby causing errors and system fai... » read more

SerDes Signal Integrity Challenges At 28Gbps And Beyond


After nearly fifty years, NRZ technology continues to pose significant challenges as data rates approach 56Gbps and refreshed standards mandate increased receiver sensitivity (down to 35 mV). With shorter unit intervals and closing eyes, triggering becomes ever more complex and requires enhanced receiver equalization such as continuous-time-linear equalization and decision feedback equalization... » read more

Biz Talk: ASICs


eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Performance Increasingly Tied To I/O


Speeding up input and output is becoming a cornerstone for improving performance and lowering power in SoCs and ASICs, particularly as scaling processors and adding more cores produce diminishing returns. While processors of all types continue to improve, the rate of improvement is slowing at each new node. Obtaining the expected 30% to 50% boost in performance and lower power no longer can ... » read more

The Challenges Of Designing 28G And 56G SerDes IP


The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a loss of 9 dB. While the baud rate is 28 Gbaud, there are now three eyes stacked on top of each other. Nevertheless, there is still demand for 35+ dB reach. This is a significant challenge which requ... » read more

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