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Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP


PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

Next-Gen SerDes Roadmap


An explosion in data is causing a series of successive bottlenecks in the data center. Priyank Shukla, product marketing manager for high-speed SerDes IP at Synopsys, digs into the performance roadmap for moving data within server racks and between different racks, where the bottlenecks are today, and how they will be addressed in the future. Related SerDes Knowledge Center Top stories... » read more

Battle Brewing Over Automotive Display Protocols


Displays are multiplying in new and future automobiles. That means a lot more display data moving around the vehicle and traveling some distance between sensor and processor. While existing protocols can handle some of the new duties, new protocols also are being developed specifically for this application. “Automotive displays are proliferating, increasing in numbers and in pixel densi... » read more

Die-To-Die Chiplet Communication


At CadenceLIVE Americas 2020, one of the most viewed videos was by Samsung Foundry's Kevin Lee and Cadence's Tom Wong, titled "Let’s Talk About Chips (Chiplets), Baby…It’s All About D2D!" They went for this title because it reminded them of the lyrics of an '80s song...which they proceeded to sing. Process and packaging trends Tom led off with a look at the trends in semiconducto... » read more

Heterogeneous Integration Using Organic Interposer Technology


As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shif... » read more

112G SerDes Modeling And Integration Considerations


The ever-increasing demand for compute power and data processing in accelerators, intelligence processing units (IPUs), GPUs, as well as training and inference SoCs is driving the adoption of 112G SerDes PHY IP solutions. Ensuring a reliable Ethernet link and efficient integration are the most essential requirements that designers need to meet. IBIS-AMI modeling can help predict SerDes link per... » read more

Re-Architecting SerDes


Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Low Power Still Leads, But Energy Emerges As Future Focus


In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

Startup Funding: November 2020


Numerous chipmakers pulled in funding in November 2020, with investors putting money into interconnects, memories, AI hardware, and quantum computing. Launching from stealth was a startup aiming to combine AI and 5G. Autonomous delivery did well, too, with one company raising a massive $500M. This month, we take a look at 28 companies that raised a collective $1.1B. Semi & design Connec... » read more

Increase In Analog Problems


Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily... » read more

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