A Conference For The Ages


The International Solid-State Circuits Conference (ISSCC) was held recently in its permanent location at the San Francisco Marriott Marquis. eSilicon had the honor of both presenting our SerDes capabilities and demonstrating the technology as well. More about that later. First, I’d like to examine the institution called ISSCC. The first ISSCC was held in 1954 in Philadelphia. Yes, 1954, thatâ... » read more

Why 56Gb/s And 112Gb/s SerDes Matter In Our Daily Social-Media-Driven Lives


Hyper-scalers and service providers are moving from 100GbE to 400GbE Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure. These transitions are driven by the increasing global IP traffic as the world becomes more connected and digital. At the same time, the decentralization of the cloud and data centers are... » read more

Getting Ready for 32 GT/s PCIe 5.0 Designs


The transition from older PCI Express (PCIe) technologies to the latest Revision 5.0 is on an accelerated path, with system-on-chip (SoC) designers seeing a much faster roll out than they did with PCIe 4.0. The recent release of version 0.9 of the PCIe 5.0 Base Specification locks in the functional changes to the specification, allowing designers to confidently start their designs. With the rap... » read more

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong


First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation. Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane sp... » read more

Supercomputers Are For Everyone


Our SerDes world tour continues. This past month, we demonstrated our 7nm 56G long-reach SerDes in Dallas and Israel. In Dallas, our demonstration included error-free operation in 56G PAM4 over a 30dB channel without forward error correction through an eye-popping five-meter cable. Many thanks to our partner Samtec for providing that cable, allowing backplane designers to now “reach beyond th... » read more

Why 56Gb/s And 112Gb/s SerDes Matter In Our Daily Social-Media-Driven Lives


Hyper-scalers and service providers are moving from 100GbE to 400GbE Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure. These transitions are driven by the increasing global IP traffic as the world becomes more connected and digital. At the same time, the decentralization of the cloud and data centers are... » read more

Die-To-Die Interconnects For Chip Disaggregation


Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin... » read more

High-Speed Serial Comms: Getting There Is Half The Fun


Last month I wrote about our 56G SerDes announcement – silicon validated and running in Rome at a major show. We had a great time at that show and got a lot of compliments about the quality and flexibility of our SerDes. These kinds of unfiltered, unsolicited customer comments are really what makes it all worthwhile. It was a gratifying and exciting time. This month, we’re at it again. O... » read more

eSilicon 7nm SerDes Hits 56Gbps


ASIC provider eSilicon focuses on high-performance devices for communications infrastructure, networking, and other data-center applications. Using 7nm TSMC pro- cess technology, it has developed ASIC-design platforms under the NeuASIC brand. Each platform includes hard and soft macros for networking applications along with a new architecture and intellectual-property (IP) library for building ... » read more

Virtual Packages Improve Signal Integrity


The 112 Gb/s generation of SerDes has brought along excessive loss within the package, around 5 dBs of loss within each monolithic package. This loss markedly reduces the usefulness of these SerDes. MCM technology has progressed to where the use of 70mm packages is routine. Non-interposer MCMs easily can use 20 or more chiplets, plus large dies and passives can be used. These MCMs have low ... » read more

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