tag: SerDes

Overcoming Signal Integrity Challenges Of 112G Connections
By Cadence - 13 Mar, 2024 - Comments: 0

One of the big challenges with 112G SerDes (and, to a lesser extent, all SerDes) is handling signal integrity issues. In the worst case of a long-reach application, the signal starts at the transmitter on one chip, goes from the chip to the package, across a trace on a printed-circuit board (PCB), through a connector, then a cable or backplane, another connector, another PCB trace, another pack... » read more

DSP Techniques For High-Speed SerDes
By Ed Sperling - 23 Oct, 2023 - Comments: 0

Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
By The SE Staff - 07 Aug, 2023 - Comments: 0

Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

224G SerDes Trend and Solution
By Yang Zhang - 27 Jul, 2023 - Comments: 0

As an industry early mover to support the emerging 800G/1.6T networks, Cadence taped out the 224G-LR SerDes PHY IP on TSMC’s 3nm process at the beginning of the year and expects the silicon to arrive soon. The IP supports 1-225Gbps data rates with excellent BER at long reach (LR). The ever-increasing bandwidth requirement in hyperscale data centers is driving the rapid growth of high-speed I/... » read more

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches
By Madhumita Sanyal - 20 Jul, 2023 - Comments: 0

The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies
By Synopsys - 07 Jun, 2023 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

Design Challenges Of High-Speed Wireline Transmitters
By Samad Parekh - 27 Apr, 2023 - Comments: 0

By Samad Parekh and Noman Hai The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25T (terabytes) to 50T and soon to 100T. The industry has chosen Ethernet to drive the switch market, using 112G SerDes technology today and next generation architectures being designed to operate at... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes
By Synopsys - 07 Dec, 2022 - Comments: 0

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

Reducing Schedule Slips With Automated Post-Route Verification Of SerDes High Speed Serial Links
By Todd Westerhoff - 01 Sep, 2022 - Comments: 1

Most high-speed serial links don’t get verified once routing is complete because the process is time consuming and skill-intensive – and SI experts are in short supply. As a result, most serial channels are laid out according to rules, verified through manual inspection, and released to fabrication without thorough analysis. Unverified channels can result in lengthy (and hectic) prototype d... » read more

Compute Express Link (CXL): All You Need To Know
By Rambus - 10 Aug, 2022 - Comments: 0

An in-depth look at Compute Express Link  (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. We discuss how CXL technology maintains memory c... » read more

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