Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes


Conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA), that are demanded of leading-edge designs. With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is a growing challenge. In this context, disaggregated architectures such as chipl... » read more

Which Chip Interconnect Protocol Is Better?


Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversation... » read more

Week In Review: Auto, Security, Pervasive Computing


AI, machine learning Cadence says it has optimized its Tensilica HiFi digital signal processor IP to efficiently execute TensorFlow Lite for Microcontrollers, which are used in Google’s machine learning platform for edge. This means developers of AI/ML on the edge systems can now put better audio processing on edge devices with ML applications like keyword detection, audio scene detection, n... » read more

Die-to-Die Connectivity With High-Speed SerDes PHY IP


Hyperscale data center, artificial intelligence (AI), and networking SoCs have become more complex with advanced functionalities and have reached maximum reticle sizes. Designers are partitioning such SoCs in smaller modules requiring ultra- and extra-short reach links for inter-die connectivity with high data rates. The die-to-die connectivity must also ensure reliable links with extremely low... » read more

Enabling Integration Success Using High-Speed SerDes IP


By Niall Sorensen and Malini Narayanammoorthi Internet traffic volumes continue to grow at a breakneck pace, and the demands on SerDes speeds increase accordingly. High-speed SerDes play an integral part of the networking chain and these speed increases are required to support the bandwidth demands of artificial intelligence (AI), Internet of Things (IoT), virtual reality (VR) and many more ... » read more

Week In Review: Design, Low Power


Xilinx filed a patent infringement countersuit against Analog Devices, alleging infringement of eight U.S. patents including technologies involving serializers/deserializers (SerDes), high-speed ADCs and DACs, as well as mixed-signal devices targeting 5G and other markets. The counterclaims are in response to Analog Devices' December lawsuit alleging unauthorized use by Xilinx of eight ADI pate... » read more

Electromagnetic Challenges In High-Speed Designs


ANSYS’ Anand Raman, senior director, and Nermin Selimovic, product sales specialist, talk with Semiconductor Engineering about how to deal with rising complexity and tighter tolerances in AI, 5G, high-speed SerDes and other chips developed at the latest process nodes where the emphasis is on high performance and low power. » read more

Die-To-Die Connectivity


Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how die-to-die communication is changing as Moore’s Law slows down, new use cases such as high-performance computing, AI SoCs, optical modules, and where the tradeoffs are for different applications.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTu... » read more

Speeding Up 3D Design


2.5D and 3D designs have garnered a lot of attention recently, but when should these solutions be considered and what are the dangers associated with them? Each new packaging option trades off one set of constraints and problems for a different set, and in some cases the gains may not be worth it. For other applications, they have no choice. The tooling in place today makes it possible to de... » read more

Accelerating Chiplets With 112G XSR SerDes PHYs


The fading of Moore’s Law and an almost exponential increase in data is challenging the semiconductor industry as never before. Indeed, zettabytes of data are constantly generated by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. Moreover, sophisticated artificial intelligence (AI) and machine learning (ML) applications are adding new ... » read more

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